ADN2892(RevPrA) データシートの表示（PDF） - Analog Devices

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ADN2892
(Rev.:RevPrA)

3.3 V 4.25 Gb/s Limiting Amplifier

Analog Devices 

ADN2892

THEORY OF OPERATION

LIMAMP

Input Buffer

The limiting amplifier has differential inputs (PIN/NIN), with

an internal 50 Ω termination. The ROSA (receive optical sub-

assembly) is typically ac-coupled to the ADN2892 inputs

(although dc coupling is possible).

There is an on-chip, input offset compensation loop with a

30kHz low-frequency cutoff.

CML Output Buffer

The ADN2892 provides CML outputs, OUTP/OUTN. The

outputs are internally terminated with 50 Ω to VCC.

The outputs can be kept at a static voltage by driving the

SQUELCH pin to a logic high. The SQUELCH pin can be

driven directly by the LOS pin, which automatically disables the

LIMAMP outputs in situations with no data input.

BANDWIDTH SELECT

The ADN2892 has an on-chip selectable 4th order Bessel-

Thomson filter in order to support 1x/2x/4x Fiber Channel

transceivers utilizing rate select. Setting the BW_SEL pin to

logic 0 selects the on-chip filter which reduces the BW of the

limamp to ~1.5GHz. This is sufficient to filter out the relaxation

oscillation from legacy 1Gb/s Fiber Channel transmitters using

CD lasers while still providing enough BW to be backwards

compatible with 1x/2x FC multi-rate SFP modules that don't

use the rate select function.

Setting the BW_SEL pin to a logic 1 sets the bandwidth of the

ADN2892 to the full BW of ~4.25GHz. This rate select protocol

is compliant with SFF-8079 Rev 1.0

Preliminary Technical Data

LOSS OF SIGNAL (LOS) DETECTOR

The receiver front-end LOS detector circuit indicates when the

input signal level has fallen below a user-adjustable threshold.

The threshold is set by a resistor connected between the

THRADJ pin and VEE. When the input level drops below this

threshold, the LOS output will assert to a logic 1. There is

hysteresis built into the LOS circuit to prevent chattering at the

LOS output. The LOS hysteresis is typically 5dB.

The LOS output is an open-drain output that needs to be

externally pulled up with a 4.7kΩ-10kΩ resistor. The LOS

output active high by default which is compliant with the SFP

and GBIC MSAs. There is an LOS_INV input which, when set

to a logic 1, inverts the LOS output so that it is active low. This

is in order to support the SFF MSA.

RECEIVED SIGNAL STRENGTH INDICATOR (RSSI)

The ADN2892 has an on-chip RSSI circuit that automatically

detects the average received power, based on a direct measure-

ment of the PIN photodiode’s current. The photodiode bias is

supplied by the ADN2892, which allows a very accurate, on-

chip, average power measurement based on the amount of

current supplied to the photodiode. The output of the RSSI is a

current that is directly proportional to the average amount of

PIN photodiode current. Placing a resistor between the

RSSI_OUT pin and GND converts the current to a GND

referenced voltage. This function eliminates the need for

external RSSI circuitry in SFF-8472 compliant optical receivers.

SQUELCH MODE

Driving the SQUELCH input to a logic high disables the

limiting amplifier outputs. The SQUELCH input can be

connected to the LOS output to keep the limiting amplifier

outputs at a static voltage level anytime the input level to the

limiting amplifier drops below the programmed LOS threshold.

Rev. PrA| Page 8 of 12

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