ADN2892(RevPrA) データシートの表示（PDF） - Analog Devices
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ADN2892 Datasheet PDF : 12 Pages
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Preliminary Technical Data
APPLICATIONS INFORMATION
PCB DESIGN GUIDELINES
Proper RF PCB design techniques must be used for optimal
performance.
Power Supply Connections and Ground Planes
Use of one low impedance ground plane is recommended. The
VEE pins should be soldered directly to the ground plane to
reduce series inductance. If the ground plane is an internal
plane and connections to the ground plane are made through
vias, multiple vias can be used in parallel to reduce the series
inductance, especially on Pin 9, which is the ground return for
the output buffers. The exposed pad should be connected to the
GND plane using filled vias so that solder does not leak through
the vias during reflow. Using filled vias under the package
ADN2892
greatly enhances the reliability of the connectivity of the
exposed pad to the GND plane during reflow.
Use of a 10 µF electrolytic capacitor between VCC and VEE is
recommended at the location where the 3.3 V supply enters the
PCB. When using 0.1 µF and 1 nF ceramic chip capacitors, they
should be placed between the IC power supply VCC and VEE,
as close as possible to the ADN2892 VCC pins.
If connections to the supply and ground are made through vias,
the use of multiple vias in parallel helps to reduce series
inductance, especially on Pin 12, which supplies power to the
high speed OUTP/ OUTN output buffers. Refer to the
schematic in Figure 8 for recommended connections.
VCC
0.1µF
ADN2882
VCC
C9
R1
RSSI measurement
to ADC
C10
VCC
C5 C6
C1
AVCC 1
PIN 2
connect
exposed
12 DRVCC
11 OUTP
C2
NIN 3
pad to
GND
10 OUTN
AVEE 4
9 DRVEE
VCC
C7 C8
C3
C4
To Host Board
C12 R2
VCC
R3 4.7k - 10k
on host board
C1-C4, C11: 0.01µF X5R/X7R dielectric, 0201 case
C5,C7,C9,C10,C12: 0.1µF X5R/X7R dielectric, 0402 case
C6, C8: 1nF X5R/X7R dielectric, 0201 case
to ADuC7020
Figure 8. Typical ADN2892 Applications Circuit
Rev. PrA | Page 9 of 12
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