ADP3025 データシートの表示（PDF） - Analog Devices

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ADP3025

High Efficiency Dual Output Power Supply Controller

Analog Devices 

ADP3025

2. Switching losses due to the limited time of switching

FB, via an internal resistor. The error amplifier creates the

transitions. This occurs due to gate drive losses of the

closed-loop voltage level for the pulse-width modulator that

upper and lower MOSFETs and the switching node

drives the external power MOSFETs. The output LC filter

capacitive losses, and through hysteresis and eddy-current

smoothes the pulse-width modulated input voltage to a dc

losses in power choke. Input and output capacitor ripple

output voltage.

current losses should also be considered switching losses.

These losses are input voltage dependent and can be

estimated as follows:

The pulse-width modulator transfer function is VOUT/VEAOUT,

where VEAOUT is the output voltage of the error amplifier. That

function is dominated by the impedance of the output filter

PSWLOSS = VIN 1.85 × IMAX × CSN × f

(19)

with its double-pole resonance frequency (fLC), a single zero at

the output capacitor (fESR), and the dc gain of the modulator; it

where CSN is the overall capacitance of the switching node

related to loss.

3. Supply current of the switching controller (independent of

the input current redirected to supply the MOSFETs’ gates).

This is a very small portion of the overall loss, but it does

E increase with input voltage.

TRANSIENT RESPONSE CONSIDERATIONS

T Both stability and regulator loop response can be checked by

looking at the load transient response. Switching regulators take

several cycles to respond to a step in output load current. When

a load step occurs, output voltage shifts by an amount equal to

E the current step multiplied by the total ESR of the summed

output capacitor array. Output overshoot or ringing during the

recovery time (in both directions of the current step change)

L indicates a stability problem. The external feedback compensa-

tion components shown in Figure 17 should provide adequate

compensation for most applications.

O PWM

COMPARATOR

S VRAMP

ADP3025

DRVH

DRVL

EAO

B EAN

OR1

VIN

L1

VOUT

COUT

C2

C1 R2

PARASITIC

ESR

C3

R3

is equal to the input voltage divided by the peak ramp height

(VRAMP), which is equal to 1.2 V when VIN = 12 V.

fLC =

1

(20)

2π × LF × COUT

fESR =

1

(21)

2π × ESR ×COUT

The compensation network consists of the internal error

amplifier and two external impedance networks, ZIN and ZFB.

Once the application and the output filter capacitance and ESR

are chosen, the specific component values of the external

impedance networks, ZIN and ZFB, can be determined. There are

two design criteria for achieving stable switching regulator

behavior within the line and load range. One is the maximum

bandwidth of the loop, which affects fast transient response, if

needed; the other is the minimum accepted by the design phase

margin.

The phase margin is the difference between the closed-loop

phase and 180°. Recommended phase margin is 45° to 60° for

most applications.

The equations to calculate the compensation poles and zeros are

fP1

=

2π

×

1

R2×

C1×C2

(22)

C1+ C2

fP 2 =

1

(23)

2π × R3×C3

REF FB

fZ1 =

1

(24)

2π × R2 × C1

Figure 18. Buck Regulator Voltage Control Loop

FEEDBACK LOOP COMPENSATION

( ) fZ2 =

1

2π × R1 × R3 × C3

(25)

The ADP3025 uses voltage mode control to stabilize the

switching controller outputs. Figure 18 shows the voltage mode

control loop for one of the buck switching regulators. The inter-

nal reference voltage, VREF, is applied to the positive input of the

internal error amplifier. The other input of the error amplifier is

EAN, and is internally connected to the feedback sensing pin,

The value of the internal resistor R1 is 74 kΩ for the 3.3 V

switching regulator and 130 kΩ for the 5 V switching regulator.

Rev. A | Page 18 of 24

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