ADP3025 データシートの表示（PDF） - Analog Devices

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ADP3025

High Efficiency Dual Output Power Supply Controller

Analog Devices 

ADP3025

Power Circuitry

12. Whenever a power dissipating component (e.g., a power

10. The switching power path should be routed on the PCB to

encompass the smallest possible area in order to minimize

radiated switching noise energy (i.e., EMI). Failure to take

proper precautions often results in EMI problems for the

entire PC system as well as noise-related operational

problems in the power converter control circuitry. The

switching power path is the loop formed by the current

MOSFET) is soldered to a PCB, the liberal use of vias, both

directly on the mounting pad and immediately surround-

ing it, is recommended. Two important reasons for this are:

improved current rating through the vias (if it is a current

path) and improved thermal performance, especially if the

vias are extended to the opposite side of the PCB where a

plane can more readily transfer the heat to the air.

path through the input capacitors, the two FETs (and the

13. The output power path, though not as critical as the

power Schottky diode, if used), including all interconnec-

switching power path, should also be routed to encompass

ting PCB traces and planes. The use of short and wide

interconnection traces is especially critical in this path for

two reasons: it minimizes the inductance in the switching

loop, which can cause high energy ringing, and it accom-

modates high current demand with minimal voltage loss.

E 11. A power Schottky diode (1 A ~ 2 A dc rating) placed from

the lower FET’s source (anode) to drain (cathode) helps to

minimize switching power dissipation in the upper FET. In

the absence of an effective Schottky diode, this dissipation

T occurs through the following sequence of switching events.

The lower FET turns off in advance of the upper FET

turning on (necessary to prevent cross-conduction). The

E circulating current in the power converter, no longer

finding a path for current through the channel of the lower

FET, draws current through the inherent body drain diode

L of the FET. The upper FET turns on, and the reverse

recovery characteristic of the lower FET’s body drain diode

prevents the drain voltage from being pulled high quickly.

The upper FET then conducts very large current while it

O momentarily has a high voltage forced across it, which

translates into added power dissipation in the upper FET.

The Schottky diode minimizes this problem by carrying a

S majority of the circulating current when the lower FET is

turned off, and by virtue of its essentially nonexistent

OB reverse recovery time.

a small area. The output power path is formed by the

current path through the inductor, the output capacitors,

and back to the input capacitors.

14. For best EMI containment, the power ground plane should

extend fully under all the power components except the

output capacitors. These are the input capacitors, the power

MOSFETs and Schottky diode, the inductor, and any

snubbing elements that might be added to dampen ringing.

Avoid extending the power ground under any other

circuitry or signal lines, including the voltage and current

sense lines.

Signal Circuitry

15. The CS and SW traces should be Kelvin-connected to the

upper MOSFET drain and source so that the additional

voltage drop due to current flow on the PCB at the current

sense comparator connections does not affect the sensed

voltage. It is desirable to have the ADP3025 close to the

output capacitor bank and not in the output power path so

that any voltage drop between the output capacitors and

the AGND pin is minimized and voltage regulation is not

compromised.

Rev. A | Page 20 of 24

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