ADP3026(RevPrB) データシートの表示（PDF） - Analog Devices

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ADP3026
(Rev.:RevPrB)

High-Efficiency Notebook Computer Power Supply Controller

Analog Devices 

PRELIMINARY TECHNICAL DATA

ADP3026

Shutdown (SD)

Holding SD = GND low will put the ADP3026 into

ultralow current shutdown mode. For automatic start-up,

SD can be tied directly to VIN.

Soft-Start and Power-Up Sequencing (SS)

SS3 and SS5 are soft-start pins for the two controllers. A

2.5 µA pull-up current is used to charge an external soft-

start capacitor. Power-up sequencing can easily be done by

choosing different capacitance. When SS3/SS5 < 0.6 V, the

two switching regulators are turned off. When 0.6 V < SS5/

SS3 < 1.8 V, the regulators start working in soft-start mode.

When SS3/SS5 > 1.8 V, the regulators are in normal oper-

ating mode. The controllers are forced to stay in PWM

mode during the soft-start period. The minimum soft-start

time (~20 µs) is set by an internal capacitor. Table II shows

the ADP3026 operating modes.

Current Limiting (CLSET)

A cycle-by-cycle current limiting scheme is used by monitor-

ing current through the top N-channel MOSFET when it is

turned on. By measuring the voltage drop across the high-side

MOSFET VDS(ON), the external sense resistor can be de-

leted. The current limit value can be set by CLSET. When

CLSET = Floating, the maximum VDS(ON) = 72 mV at

room temperature; when CLSET = 0 V, the maximum

VDS(ON) = 300 mV at room temperature. An external resistor

can be connected between CLSET and AGND to choose a

value between 72 mV and 300 mV. The relationship between

the external resistance and the maximum VDS(ON) is:

VDS(ON )MAX

=

72 mV

(110K + REXT )

(26K + REXT )

(1)

The temperature coefficient of RDS(ON) of the N-channel

MOSFET is canceled by the internal current limit circuitry,

so that an accurate current limit value can be obtained

over a wide temperature range. In PSV mode, the current

limit value is reduced to about 1/4 of the value in PWM

mode to reduce the interference noise to other components

on the PC board.

Output Undervoltage Protection

Each switching controller has an undervoltage protection

circuit. When the current flowing through the high-side

MOSFET reaches the current limit continuously for eight

clock cycles, and the output voltage is below 20% of the

nominal output voltage, both controllers will be latched

off and will not restart until SD or SS3/SS5 is toggled, or

until VIN is cycled below 4 V. This feature is disabled during

soft start.

Output Overvoltage Protection

Both converter outputs are continuously monitored for ov-

ervoltage. If either output voltage is higher than the nominal

output voltage by more than 20%, both converter’s high-side

gate drivers (DRVH5/3) will be latched off, and the low-

side gate drivers will be latched on, and will not restart until

SD or SS5/SS3 are toggled, or until VIN is cycled below 4

V. The low-side gate driver (DRVL) is kept high when

the controller is in off-state and the output voltage is less

than 93% of the nominal output voltage. Discharging the

output capacitors through the main inductor and low-side

N-channel MOSFET will cause the output to ring. This

will make the output momentarily go below GND. To

prevent damage to the circuit, use a reverse-biased 1 A

Schottky diode across the output capacitors to clamp the

negative surge.

Power Good Output (PWRGD)

The ADP3026 also provides a PWRGD signal for the mi-

croprocessor. During start-up, the PWRGD pin is held low

until 5 V output is within –3% of its preset voltage. Then,

after a time delay determined by an external timing ca-

pacitor connected from CPOR to GND, PWRGD will be

actively pulled up to INTVCC by an external pull-up resis-

tor. This delay can be calcualated by:

Td = 1.2V ×CCPOR

1µA

(2)

CPOR can also be used as a manual reset (MR) function.

When the 5 V output is lower than the preset voltage by

more than 7%, PWRGD is immediately pulled low.

APPLICATION INFORMATION

A typical notebook PC application circuit using the

ADP3026 is shown in Figure 2. Although the component val-

ues given in Figure 3 are based on a 5 V @ 4 A /3.3 V @

4 A design, the ADP3026 output drivers are capable of

SD

Low

High

High

High

High

High

Table II. Operating Modes

SS5

X

SS5 < 0.6 V

0.6 V < SS5 < 1.8 V

1.8 V < SS5

X

X

SS3

X

SS3 < 0.6 V

X

X

0.6 V < SS3 < 1.8 V

1.8 V < SS3

Mode

Shutdown

Standby

Run

Run

Run

Run

Description

All Circuits Turned Off

5 V and 3.3 V Off; INTVCC = 5 V, REF = 0.8 V

5 V in Soft Start

5 V in Normal Operation

3.3 V in Soft Start

3.3 V in Normal Operation

REV. PrB

–11–

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