ADP3050 データシートの表示（PDF） - Analog Devices
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ADP3050 Datasheet PDF : 20 Pages
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ADP3050
THEORY OF OPERATION
The ADP3050 is a fixed frequency, current mode buck regulator.
Current mode systems provide excellent transient response, and
are much easier to compensate than voltage mode systems (refer to
Figure 1). At the beginning of each clock cycle, the oscillator
sets the latch, turning on the power switch. The signal at the
noninverting input of the comparator is a replica of the switch
current (summed with the oscillator ramp). When this signal
reaches the appropriate level set by the output of the error amplifier,
the comparator resets the latch and turns off the power switch. In
this manner, the error amplifier sets the correct current trip
level to keep the output in regulation. If the error amplifier
output increases, more current is delivered to the output; if it
decreases, less current is delivered to the output.
The current sense amplifier provides a signal proportional to
switch current to both the comparator and to a cycle-by-cycle
current limit. If the current limit is exceeded, the latch is reset,
turning the switch off until the beginning of the next clock
cycle. The ADP3050 has a foldback current limit that reduces
the switching frequency under fault conditions to reduce stress
to the IC and to the external components.
Most of the control circuitry is biased from the 2.5 V internal
regulator. When the BIAS pin is left open, or when the voltage
at this pin is less than 2.7 V, all of the operating current for the
ADP3050 is drawn from the input supply. When the BIAS pin is
above 2.7 V, the majority of the operating current is drawn from
this pin (usually tied to the low voltage output of the regulator)
instead of from the higher voltage input supply. This can provide
substantial efficiency improvements at light load conditions,
especially for systems where the input voltage is much higher
than the output voltage.
The ADP3050 uses a special drive stage allowing the power
switch to saturate. An external diode and capacitor provide a
boosted voltage to the drive stage that is higher than the input
supply voltage. Overall efficiency is dramatically improved by
using this type of saturating drive stage.
Pulling the SD pin below 0.4 V puts the device in a low power
mode, shutting off all internal circuitry and reducing the supply
current to under 20 μA.
Data Sheet
L1
33µH
D1
1N5818
D2
1N4148
C3
220nF
12V
VIN
+ C1
22µF
1 SWITCH IN 8
2 BOOST GND 7
3 BIAS
SD 6
4 FB COMP 5
U1
ADP3050-3.3
3.3V
VOUT
+ C4
100µF
R1
4kΩ
C2
1nF
Figure 24. Typical Application Circuit
SETTING THE OUTPUT VOLTAGE
The output of the adjustable version (ADP3050AR and
ADP3050ARZ) can be set to any voltage between 1.25 V and 12 V
by connecting a resistor divider to the FB pin as shown in
Figure 25.
R2
=
R1
×
VOUT
1.2
− 1
L1
22µH
D1
1N5817
C3
0.22µF
1 SWITCH IN 8
2 BOOST GND 7
(1)
2.5V
VOUT
+ C4
2×22µF
CERAMIC
CF
R2
21.5kΩ
3 BIAS
SD 6
D2
1N4148
5V
VIN
GND
R1
20kΩ
4 FB COMP 5
U1
ADP3050
RC
7.5kΩ
CC
4.7nF
+ C1
2×10µF
CERAMIC
C2
0.01µF
Figure 25. Adjustable Output Application Circuit
Rev. C | Page 10 of 20
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