ADP3088 データシートの表示（PDF） - Analog Devices
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ADP3088 Datasheet PDF : 11 Pages
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ADP3088
PRELIMINARY TECHNICAL DATA
output voltage within a ~100 mV range with only a 4.7 µF
output capacitor, even when the load slew rate is extremely
fast. This does not include the initial tolerance of the volt-
age setting that is separately accounted with voltage posi-
tioning designs. Note that the lower resistor, RB, of the
feedback divider is reduced from the 10 kΩ value that one
would use for a standard (non-voltage-positioned) design
that had no voltage positioning resistor RVP.
3.3V
1µF
MLCC
CHF
4.7pF
ADP3088
IN
SW
IN
DRV
GND GND
COMP FB
RVP
51kΩ
3.3µH
1A
4.7µF
SCHOTTKY MLCC
-2.5V
100-400 mA
RA
10kΩ
RB
8.75kΩ
Figure 4. Application Circuit using Voltage Positioning,
Allowing Small Output Capacitance
Extra-Low-Voltage Outputs
Some newer power management applications require volt-
age levels below the normal adjustable voltage range of the
ADP3088, i.e., below 1.25 V. Such applications can be
accommodated using the ADP3088 by modifying the appli-
cation circuit to sum in a resistor-weighted portion of an-
other regulated system voltage, e.g., 3.3 V, to the feedback
node (FB). The tolerance of the ADP3088's output voltage
will increase by an amount proportional to the tolerance of
the summed in system voltage times the ratio of the con-
ductance from that node to that of the output voltage. The
below example in Figure 5 shows an implementation of this
technique together with another special implementation
described below. The resistor RTT sums from a 2.5 V sys-
tem voltage to the FB node that will reduce the output volt-
age according to the formula:
∆VOUT
=
−VTT
×
RA
RTT
(19)
Dynamic Voltage Control
Some newer power management applications also require
an ability to adjust the voltage being delivered to a load
during operation. Although there is no integration of this
feature in the ADP3088, it can readily be accommodated
with a few components. Dynamic voltage control can be
implemented either by parallel bus control or by PWM. In
both cases, the output voltage is modified by summing
either switched bits with, presumably binary, weighting
resistors or a switched PWM node via a single resistor into
the FB pin. (The switched PWM node refers to an external
PWM control signal, not the switched node of the power
converter itself.) Since the PWM technique modulates a
current into the FB node, it is necessary both to integrate
that signal and to avoid slowing down the response of the
power converter to output voltage transitions. This can be
accomplished by placing a capacitor between the output
voltage and the feedback node, which serves to provide a
zero/pole pair in the main regulation loop, and appears as
an integration pole to the PWM signal.
The design of either parallel bit or PWM type of voltage
control must consider whether the interface node(s) - from
parallel switched bits or a single PWM signal - has an active
pullup state (in which case it must be to a known voltage)
or a passive pullup (open drain) that floats up to the FB
node voltage, 1.25 V, in its high state. If at least the lower
extreme of the desired output voltage range must be lower
than 1.25 V, either technique can be combined with the
technique for lowering the output voltage below 1.25 V.
Such an example of an application having this requirement
is the BlackFin™ DSP. Figure 5 shows an implementation
of this technique.
Input Voltage: 4.75 V ~ 7.5 V
Output Voltage: 0.9 V ~ 1.5 V
Dynamic voltage control interface technique: PWM,
active high to VIO
System voltage used for lowering output voltage below
1.25 V: VTT = VIO = 2.5 V
Maximum output current: 700 mA
VIN
5V - 8V
2.2µF
MLCC
ADP3088
IN
SW
IN
DRV
GND GND
CHF
10pF
CC
COMP
FB
470pF
RC
20kΩ
10µH @ 1A
1N5817
3×10µF
MLCC
VOUT
0.9V-1.5V
@700 mA
CFF
2.2nF
RA
10.0kΩ
RTT
287kΩ
VTT 2.5V
PWM 0-2.5V
RPWM
41.2kΩ
Figure 5. BlackFin DSP Application
–10–
REV. PrK
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