ADP3178 データシートの表示（PDF） - Analog Devices

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ADP3178

4-Bit Programmable Synchronous Buck Controllers

Analog Devices 

ADP3158/ADP3178

100

90

80

70

60

50

40

30

20

10

0

02 4

6

8 10 12 14 16 18 20

OUTPUT CURRENT – A

Figure 5. Efficiency vs. Load Current of the Circuit

of Figure 3

To correctly implement active voltage positioning, the low fre-

quency output impedance (i.e., the output resistance) of the

converter should be made equal to the maximum ESR of the

output capacitor array. This can be achieved by having a single-

pole roll-off of the voltage gain of the gm error amplifier, where

the pole frequency coincides with the ESR zero of the output

capacitor. A gain with single-pole roll-off requires that the gm

amplifier output pin be terminated by the parallel combination

of a resistor and capacitor. The required resistor value can be

calculated from the equation:

RCOMP

=

ROGM

ROGM

× RTOTAL

– RTOTAL

= 1 MΩ × 9.1 kΩ

1 MΩ – 9.1 kΩ

= 9.2 kΩ

where:

RTOTAL

=

nI × RSENSE

gm × RE ( MAX )

=

25 × 4 mΩ

2.2 mmho × 5 mΩ

= 9.1 kΩ

(24)

(25)

In Equations 24 and 25, ROGM is the internal resistance of the gm

amplifier, nI is the division ratio from the output voltage to

signal of the gm amplifier to the PWM comparator, and gm is the

transconductance of the gm amplifier itself.

Although a single termination resistor equal to RCOMP would yield

the proper voltage positioning gain, the dc biasing of that resistor

would determine how the regulation band is centered (i.e., offset).

Note that sometimes the specified regulation band is asymmetrical

with respect to the nominal VID voltage. With the ADP3158 and

ADP3178, the offset is already considered part of the design

procedure—no special provision is required. To accomplish the dc

biasing, it is simplest to use two resistors to terminate the gm

amplifier output, with the lower resistor (RB) tied to ground and

the upper resistor (RA) to the 12 V supply of the IC. The values of

these resistors can be calculated using:

RA

=

gm

VDIV

× (VOUT (OS )

+

K)

=

12V

2.2 mmho × (22 mV

+ 4.7 × 10–2 )

=

79.1 kΩ

(26)

where K is a constant determined by internal characteristics of the

ADP3158 and ADP3178, peak-to-peak inductor current ripple

(IRIPPLE), and the current sampling resistor (RSENSE). K can be

calculated using Equations 28 and 29. VDIV is the resistor divider

supply voltage (e.g., the recommended 12 V supply) and VOUT(OS) is

the output voltage offset from the nominal VID-programmed value

under no load condition. This offset is given by Equation 30.

The closest 1% value for RA is 78.7 kΩ. This value is then used

to solve for RB:

RB

=

RA × RCOMP

RA – RCOMP

= 78.7 kΩ × 9.2 kΩ

78.7 kΩ – 9.2 kΩ

= 10.4 kΩ

The nearest 1% value of 10.5 kΩ was chosen for RB.

K

=





I L(RIPPLE

2

)

×

(RSENSE × nI )

gm × RTOTAL 

+

gm

VGNL

× RTOTAL

–

VCC

2 × gm ROGM

(27)

(28)

K

=





3.8

2

A

×

4 mΩ × 25

2.2 mmho × 9.1 kΩ





+

1.174

2.2 mmho × 9.1 kΩ

−

12V

2 × 2.2 mmho × 130 kΩ

= 4.7 × 10–2

VGNL

= VGNL0

+

IL(RIPPLE )

× RSENSE

2

× nI

− VIN

− VVID

L

× tD

× RSENSE

×

nI





(29)

VGNL

= 1V

+

3.8

A

×

4 mΩ

2

×

25

−

 5V –

 1.5

1.7 V

µH

×

75

ns

×

4

mΩ

×



25

= 1.174V

( ) VOUT (OS ) = VOUT ( MAX ) − VVID

−

RE ( MAX )

× I L( RIPPLE )

2

− VVID

× kVID

VOUT (OS )

=

40

mV

−

5

mΩ

× 3.8

2

A

− 1.7V

× 5 × 10–3

=

22

mV

(30)

Finally, the compensating capacitance is determined from the

equality of the pole frequency of the error amplifier gain and the

zero frequency of the impedance of the output capacitor:

COC

=

COUT × ESR

RTOTAL

=

5 mF × 4.8 mΩ

9.1 kΩ

= 2.6

nF

(31)

The closest standard value for COC is 2.7 nF.

REV. A

–11–

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