ADP3179JRU データシートの表示（PDF） - Analog Devices
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ADP3179JRU Datasheet PDF : 16 Pages
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ADP3159/ADP3179
Surface mount MOSFETs are preferred in CPU core converter
applications due to their ability to be handled by automatic
assembly equipment. The TO-263 package offers the power
handling of a TO-220 in a surface-mount package. However,
this package still needs adequate copper area on the PCB to
help move the heat away from the package.
The junction temperature for a given area of 2-ounce copper
can be approximated using:
( ) TJ = θJA × PD + TA
(21)
assuming:
θJA = 45°C/W for 0.5 in2
θJA = 36°C/W for 1 in2
θJA = 28°C/W for 2 in2
For 1 in2 of copper area attached to each transistor and an
ambient temperature of 50°C:
TJHSF = (36°C/W × 1.48 W ) + 50°C = 103°C
TJLSF = (36°C/W × 1.08 W ) + 50°C = 89°C
All of the above-calculated junction temperatures are safely
below the 175°C maximum specified junction temperature of
the selected MOSFETs.
CIN Selection and Input Current di/dt Reduction
In continuous inductor-current mode, the source current of the
high-side MOSFET is approximately a square wave with a duty
ratio equal to VOUT/VIN and an amplitude of one-half of the
maximum output current. To prevent large voltage transients, a
low ESR input capacitor sized for the maximum rms current
must be used. The maximum rms capacitor current is given by:
IC(RMS ) = IO DHSF − DHSF 2 =
(22)
15 A 0.36 – 0.362 = 7.2 A
For a ZA-type capacitor with 1000 µF capacitance and 6.3 V
voltage rating, the ESR is 24 mΩ and the maximum allowable
ripple current at 100 kHz is 2 A. At 105°C, at least four such
capacitors must be connected in parallel to handle the calculated
ripple current. At 50°C ambient, however, a higher ripple cur-
rent can be tolerated, so three capacitors in parallel are adequate.
The ripple voltage across the three paralleled capacitors is:
VC( IN )RIPPLE
=
IO
×
ESRC
nC
(
IN
)
+
nC
DHSF
× CIN ×
f MAX
VC( IN )RIPPLE
= 15
A
×
24
mΩ
3
+
36%
3 × 1000 µF × 195 kHz
= 129 mV
(23)
To further reduce the effect of the ripple voltage on the system
supply voltage bus, and to reduce the input-current di/dt to
below the recommended maximum of 0.1 A/ms, an additional
small inductor (L > 1 µH @ 10 A) should be inserted between
the converter and the supply bus.
Feedback Compensation for Active Voltage Positioning
Optimized compensation of the ADP3159 allows the best pos-
sible containment of the peak-to-peak output voltage deviation.
Any practical switching power converter is inherently limited by
the inductor in its output current slew rate to a value much less
than the slew rate of the load. Therefore, any sudden change of
load current will initially flow through the output capacitors,
and this will produce an output voltage deviation equal to the
ESR of the output capacitor array times the load current change.
TEK RUN: 200kS/s SAMPLE TRIG'D
2
CH1 100mV
CH2 M 250s
CH2
680mV
Figure 4. Transient Response of the Circuit of Figure 3
100
90
80
70
60
50
40
30
20
10
0
02
4
6
8 10 12 14 16 18 20
OUTPUT CURRENT – A
Figure 5. Efficiency vs. Load Current of the Circuit
of Figure 3
To correctly implement active voltage positioning, the low fre-
quency output impedance (i.e., the output resistance) of the
converter should be made equal to the maximum ESR of the
output capacitor array. This can be achieved by having a single-
pole roll-off of the voltage gain of the gm error amplifier, where
the pole frequency coincides with the ESR zero of the output
capacitor. A gain with single-pole roll-off requires that the gm
amplifier output pin be terminated by the parallel combination
of a resistor and capacitor. The required resistor value can be
calculated from the equation:
RCOMP
=
ROGM × RTOTAL
ROGM – RTOTAL
= 1 MΩ × 9.1 kΩ
1 MΩ – 9.1 kΩ
= 9.2 kΩ
where:
RTOTAL
=
nI × RSENSE
gm × RE ( MAX )
=
25 × 4 mΩ
2.2 mmho × 5 mΩ
=
9.1 kΩ
(24)
(25)
In Equations 24 and 25, ROGM is the internal resistance of the
gm amplifier, nI is the division ratio from the output voltage to
signal of the gm amplifier to the PWM comparator, and gm is the
transconductance of the gm amplifier itself.
–10–
REV. A
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