ADP3179JRU データシートの表示（PDF） - Analog Devices
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ADP3179JRU Datasheet PDF : 16 Pages
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ADP3159/ADP3179
APPLICATION INFORMATION
Specifications for a Design Example
The design parameters for a typical 750 MHz Pentium III appli-
cation (shown in Figure 3) are as follows:
Input Voltage: (VIN) = 5 V
Auxiliary Input: (VCC) = 12 V
Output Voltage (VVID) = 1.7 V
Maximum Output Current (IO(MAX)) = 15 A
Minimum Output Current (IO(MIN)) = 1 A
Static tolerance of the supply voltage for the processor core
(∆VO) = +40 mV (–80 mV) = 120 mV
Transient tolerance (for less than 2 µs) of the supply voltage
for the processor core when the load changes between the
minimum and maximum values with a di/dt of 20 A/µs
(∆VO(TRANSIENT)) = +80 mV (–130 mV) = 210 mV
Input current di/dt when the load changes between the mini-
mum and maximum values < 0.1 A/µs.
The above requirements correspond to Intel’s published power
supply requirements based on VRM 8.4 guidelines.
CT Selection for Operating Frequency
The ADP3159 uses a constant off-time architecture with tOFF
determined by an external timing capacitor CT. Each time the
high-side N-channel MOSFET switch turns on, the voltage across
CT is reset to 0 V. During the off-time, CT is discharged by a
constant current of 150 µA. Once CT reaches 3.0 V, a new
on-time cycle is initiated. The value of the off-time is calculated
using the continuous-mode operating frequency. Assuming a
nominal operating frequency (fNOM) of 200 kHz at an output
voltage of 1.7 V, the corresponding off-time is:
RSENSE is the resistance of the sense resistor
(estimated value: 4 mΩ)
RL is the resistance of the inductor
(estimated value: 3 mΩ)
Inductance Selection
The choice of inductance determines the ripple current in the
inductor. Less inductance leads to more ripple current, which
increases the output ripple voltage and the conduction losses in
the MOSFETs, but allows using smaller-size inductors and, for
a specified peak-to-peak transient deviation, output capacitors
with less total capacitance. Conversely, a higher inductance means
lower ripple current and reduced conduction losses, but requires
larger-size inductors and more output capacitance for the same
peak-to-peak transient deviation. The following equation shows
the relationship between the inductance, oscillator frequency,
peak-to-peak ripple current in an inductor and input and
output voltages.
L = VOUT × tOFF
IL(RIPPLE )
(4)
For 4 A peak-to-peak ripple current, which corresponds to
approximately 25% of the 15 A full-load dc current in an induc-
tor, Equation 4 yields an inductance of:
L = 1.7V × 3.3 µs = 1.4 µH
4A
A 1.5 µH inductor can be used, which gives a calculated ripple
current of 3.8 A at no load. The inductor should not saturate at
the peak current of 17 A and should be able to handle the sum
of the power dissipation caused by the average current of 15 A
in the winding and the core loss.
tOFF
=
1 –
VOUT
VIN
×
1
fNOM
tOFF
=
1
−
1.7 V
5V
×
1
200 kHz
=
3.3 µs
(1)
The timing capacitor can be calculated from the equation:
CT
= tOFF × ICT
VT (TH )
= 3.3 µs × 150 µA ≈ 150 pF
3V
(2)
Designing an Inductor
Once the inductance is known, the next step is either to design an
inductor or find a standard inductor that comes as close as
possible to meeting the overall design goals. The first decision
in designing the inductor is to choose the core material. There
are several possibilities for providing low core loss at high frequen-
cies. Two examples are the powder cores (e.g., Kool-Mµ® from
Magnetics, Inc.) and the gapped soft ferrite cores (e.g., 3F3 or 3F4
from Philips). Low frequency powdered iron cores should be
avoided due to their high core loss, especially when the inductor
value is relatively low and the ripple current is high.
The converter only operates at the nominal operating frequency
at the above-specified VOUT and at light load. At higher values
of VOUT, or under heavy load, the operating frequency decreases
due to the parasitic voltage drops across the power devices. The
actual minimum frequency at VOUT = 1.7 V is calculated to be
195 kHz (see Equation 3), where:
RDS(ON)HSF is the resistance of the high-side MOSFET
(estimated value: 14 mΩ)
Two main core types can be used in this application. Open
magnetic loop types, such as beads, beads on leads, and rods
and slugs, provide lower cost but do not have a focused mag-
netic field in the core. The radiated EMI from the distributed
magnetic field may create problems with noise interference in
the circuitry surrounding the inductor. Closed-loop types, such
as pot cores, PQ, U, and E cores, or toroids, cost more, but
have much better EMI/RFI performance. A good compromise
between price and performance are cores with a toroidal shape.
RDS(ON)LSF is the resistance of the low-side MOSFET
(estimated value: 6 mΩ)
f MIN
=
1
tOFF
×
VIN – IO( MAX ) × (RDS(ON )HSF + RSENSE + RL ) – VOUT
VIN – IO( MAX ) × (RDS(ON )HSF + RSENSE + RL – RDS(ON )LSF ))
(3)
REV. A
–7–
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