ADP3331 データシートの表示（PDF） - Analog Devices
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ADP3331 Datasheet PDF : 8 Pages
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ADP3331
VIN
C1 +
0.47F
ERR
ADP3331
OUT
IN
FB
SD
GND
R3
R1 RNR
CNR
EOUT
VOUT
+C2
0.47F
R2
ON
OFF
Figure 21. Noise Reduction Circuit
Output Voltage
The ADP3331 has an adjustable output voltage that can be set
by an external resistor divider. The output voltage will be di-
vided by R1 and R2, and then fed back to the FB pin. Refer to
Figure 21.
In order to have the lowest possible sensitivity of the output
voltage to temperature variations, it is important that the paral-
lel resistance of R1 and R2 is always 230 kΩ:
R1 ×
R1 +
R2
R2
=
230
kΩ
Also, for the best accuracy over temperature the feedback volt-
age should set for 1.204 V:
R2
VOUT R1 + R2
= VFB
where VOUT is the desired output voltage and VFB is the “virtual
bandgap” voltage. Note that VFB does not actually appear at the
FB pin due to loading by the internal PTAT current.
Combining the above equations and solving for R1 and R2 gives
the following formulas:
divider network to achieve the best performance. Using stan-
dard values as shown in Table I will sacrifice some temperature
stability.
Output Current Limit
The ADP3331 is short circuit protected by limiting the pass
transistor’s base drive current. The maximum output current is
limited to about 300 mA.
Thermal Overload Protection
The ADP3331 is protected against damage due to excessive
power dissipation by its thermal overload protection circuit.
Thermal protection limits the die temperature to a maximum of
+165°C. Under extreme conditions (i.e., high ambient tempera-
ture and power dissipation) where the die temperature starts to
rise above +165°C, the output current will be reduced until the
die temperature has dropped to a safe level.
Current and thermal limit protections are intended to protect
the device against accidental overload conditions. For normal
operation, the device’s power dissipation should be externally
limited so that the junction temperature will not exceed 125°C.
Chip-on-Lead
The ADP3331 uses a patented Chip-on-Lead package design to
ensure the best thermal performance in an SOT-23 footprint.
The standard SOT-23 depends on the majority of the heat to
flow out of the ground pin. The Chip-on-Lead package uses an
electrically isolated die attach, which allows all the pins to
contribute to heat conduction. This technique reduces the ther-
mal resistance to 190°C/W on a 2-layer board as compared to
>230°C/W for a standard SOT-23 lead frame. Figure 22 shows
the difference between the standard SOT-23 and the Chip-on-
Lead lead frames.
R1
=
230
VOUT
VFB
kΩ
R2 = 230 kΩ
1
−
VFB
VOUT
SILICON
DIE
SILICON DIE
WITH
ELECTRICALLY
ISOLATED
DIE ATTACH
NORMAL SOT-23-6 PACKAGE
THERMALLY ENHANCED
CHIP-ON-LEAD PACKAGE
Figure 22.␣ Chip-on-Lead Package
The output voltage can be adjusted to any voltage from 1.5 V to
10 V. For example, the Feedback Resistor Selection Table shows
some representative feedback resistor values for output voltages
in the specified range.
Table I. Feedback Resistor Selection
VOUT
1.5 V
1.8 V
2.2 V
2.7 V
3.3 V
5V
9V
R1 (1% Resistor)
243 kΩ
340 kΩ
422 kΩ
511 kΩ
634 kΩ
953 kΩ
1.00 MΩ
R2 (1% Resistor)
1.00 MΩ
698 kΩ
511 kΩ
412 kΩ
365 kΩ
301 kΩ
154 kΩ
Output voltages above 5 V and below 1.6 V will require non-
standard resistor values or adding an additional resistor to the
Calculating Junction Temperature
Device power dissipation is calculated as follows:
PD = (VIN – VOUT) ILOAD + (VIN) IGND
Where ILOAD and IGND are load current and ground current, VIN
and VOUT are the input and output voltages respectively.
Assuming the worst case operating conditions are ILOAD =
200 mA, IGND = 4 mA, VIN = 4.2 V and VOUT = 3.0 V, the
device power dissipation is:
PD = (4.2 V – 3.0 V) 200 mA + (4.2 V) 4 mA = 257 mW
The proprietary package used on the ADP3331 has a thermal
resistance of 165°C/W when placed on a 4-layer board, and
190°C/W when placed on a 2-layer board. This allows the ambi-
ent temperature to be significantly higher for a given power
dissipation than with a standard package. Assuming a 4-layer
board, the junction temperature rise above ambient will be
approximately equal to:
∆TJA = 0.257 W × 165°C/W = 42.4°C
REV. 0
–7–
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