ADP3330(RevC) データシートの表示（PDF） - Analog Devices

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ADP3330
(Rev.:RevC)

High Accuracy, Ultralow IQ, 200 mA, SOT-23, anyCAP Low Dropout Regulator

Analog Devices 

ADP3330

THEORY OF OPERATION

The anyCAP low dropout (LDO) ADP3330 uses a single control

loop for regulation and reference functions. The output voltage

is sensed by a resistive voltage divider consisting of R1 and R2,

which is varied to provide the available output voltage options.

Feedback is taken from this network by way of a series diode

(D1) and a second resistor divider (R3 and R4) to the input of

an amplifier.

INPUT

OUTPUT

Q1

COMPENSATION

CAPACITOR

ATTENUATION R1

(VBAND GAP/VOUT)

NONINVERTING

WIDEBAND

PTAT

gm

VOS

R3 D1

(a)

DRIVER

PTAT

ADP3330

R4

CURRENT

R2

CLOAD

RLOAD

GND

Figure 22. Functional Block Diagram

A very high gain error amplifier is used to control this loop. The

amplifier is constructed in such a way that, at equilibrium, the

amplifier produces a large, temperature proportional input

offset voltage that is repeatable and very well controlled. The

temperature proportional offset voltage is combined with the

complementary diode voltage to form a virtual band gap

voltage, implicit in the network, although it never appears

explicitly in the circuit. Ultimately, this patented design makes it

possible to control the loop with only one amplifier. This

technique also improves the noise characteristics of the

amplifier by providing more flexibility on the trade-off of noise

sources that leads to a low noise design.

The R1, R2 divider is chosen in the same ratio as the band gap

voltage to the output voltage. Although the R1, R2 resistor

divider is loaded by the D1 diode and a second divider

consisting of R3 and R4, the values are chosen to produce a

temperature stable output. This unique arrangement specifically

corrects the loading of the divider so that the typical error

resulting from base current loading in conventional circuits is

avoided.

Data Sheet

The patented amplifier controls a new and unique noninverting

driver that drives the pass transistor, Q1. The use of this

noninverting driver enables the frequency compensation to

include the load capacitor in a pole splitting arrangement to

achieve reduced sensitivity to the value, type, and ESR of the

load capacitance.

Most LDOs place strict requirements on the range of ESR values

for the output capacitor because they are difficult to stabilize,

due to the uncertainty of load capacitance and resistance.

Moreover, the ESR value required to keep conventional LDOs

stable changes depending on load and temperature. These ESR

limitations make designing with LDOs more difficult because of

their unclear specifications and extreme variations over

temperature.

The ADP3330 anyCAP LDO overcomes these limitations. It can

be used with virtually any good quality capacitor, with no

constraint on the minimum ESR. The innovative design allows

the circuit to be stable with just a small 0.47 µF capacitor on the

output. Additional advantages of the pole splitting scheme

include superior line noise rejection and very high regulator

gain, which leads to excellent line and load regulation. An

impressive ±1.4% accuracy is guaranteed over line, load and

temperature.

Additional features of the circuit include current limit, thermal

shutdown, and noise reduction. Compared to standard

solutions that give warning after the output has lost regulation,

the ADP3330 provides improved system performance by

enabling the ERR pin to give warning just before the device

loses regulation.

When the temperature of the chip rises to more than 165°C, the

circuit activates a soft thermal shutdown, indicated by a signal

low on the ERR pin, to reduce the current to a safe level.

Rev. C | Page 10 of 16

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