ADT7460(2013) データシートの表示（PDF） - ON Semiconductor

部品番号

コンポーネント説明

メーカー

ADT7460
(Rev.:2013)

Remote Thermal Monitor and Fan Controller

ON Semiconductor 

ADT7460

F4P = 1, FAN 4 OR THERM

TIMER IS OUT-OF-LIMIT

Figure 33. Status Register 2

Table 25. STATUS REGISTER 2 (REG. 0X42)

Bit Mnemonic

Description

7

D2

1 indicates an open or short on

D2+/D2− inputs.

6

D1

1 indicates an open or short on

D2+/D2− inputs.

5

F4P

1 indicates that Fan 4 has dropped

below minimum speed. Alternatively,

indicates that THERM timer limit has

been exceeded if the THERM timer

function is used.

4

FAN3

1 indicates that Fan 3 has dropped

below minimum speed.

3

FAN2

1 indicates that Fan 2 has dropped

below minimum speed.

2

FAN1

1 indicates that Fan 1 has dropped

below minimum speed.

1

OVT

1 indicates that a THERM

overtemperature limit has been

exceeded.

0

−

Unused

SMBALERT Interrupt Behavior

The ADT7460 can be polled for status, or an SMBALERT

interrupt can be generated for out-of-limit conditions. It is

important to note how the SMBALERT output and status

bits behave when writing interrupt handler software.

HIGH LIMIT

TEMPERATURE

“STICKY”

STATUS BIT

SMBALERT

TEMP BACK IN LIMIT

(STATUS BIT STAYS SET)

CLEARED ON READ

(TEMP BELOW LIMIT)

Figure 34. SMBALERT and Status Bit Behavior

Figure 34 shows how the SMBALERT output and sticky

status bits behave. Once a limit is exceeded, the

corresponding status bit is set to 1. The status bit remains set

until the error condition subsides and the status register is

read. The status bits are referred to as sticky since they

remain set until read by software. This ensures that an

out-of-limit event cannot be missed if software is polling the

device periodically. Note that the SMBALERT output

remains low for the entire duration that a reading is

out-of-limit and until the status register has been read. This

has implications on how software handles the interrupt.

Handling SMBALERT Interrupts

To prevent the system from being tied up servicing

interrupts, it is recommend to handle the SMBALERT

interrupt as follows:

1. Detect the SMBALERT assertion.

2. Enter the interrupt handler.

3. Read the status registers to identify the interrupt

source.

4. Mask the interrupt source by setting the

appropriate mask bit in the interrupt mask registers

(Reg. 0x74, 0x75).

5. Take the appropriate action for a given interrupt

source.

6. Exit the interrupt handler.

7. Periodically poll the status registers. If the

interrupt status bit has cleared, reset the

corresponding interrupt mask bit to 0. This causes

the SMBALERT output and status bits to behave

as shown in Figure 35.

HIGH LIMIT

TEMPERATURE

“STICKY”

STATUS BIT

CLEARED ON READ

(TEMP BELOW LIMIT)

TEMP BACK IN LIMIT

(STATUS BIT STAYS SET)

SMBALERT

INTERRUPT

MASK BIT SET

INTERRUPT MASK BIT

CLEARED

(SMBALERT REARMED)

Figure 35. How Masking the Interrupt Source Affects

SMBALERT Output

Masking Interrupt Sources

Interrupt Mask Registers 1 and 2 are located at Addresses

0x74 and 0x75. These allow individual interrupt sources to

be masked out to prevent SMBALERT interrupts. Note that

masking an interrupt source prevents only the SMBALERT

output from being asserted; the appropriate status bit is set

as normal.

http://onsemi.com

20

Share Link: