DatasheetQ Logo
Electronic component search and free download site. Transistors,MosFET ,Diode,Integrated circuits

ADT7460ARQZ-RL7 データシートの表示(PDF) - ON Semiconductor

部品番号
コンポーネント説明
メーカー
ADT7460ARQZ-RL7
ON-Semiconductor
ON Semiconductor ON-Semiconductor
ADT7460ARQZ-RL7 Datasheet PDF : 46 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
ADT7460
ELECTRICAL CHARACTERISTICS TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted.
Parameter (Note 1)
Test Conditions/Comments
Min Typ (Note 2) Max
Unit
DIGITAL INPUT LOGIC LEVELS (THERM)
Input High Voltage, VIH
Input Low Voltage, VIL
DIGITAL INPUT CURRENT
1.7
V
0.8
V
Input High Current, IIH
Input Low Current, IIL
Input Capacitance, CIN
SERIAL BUS TIMING (Note 4)
VIN = VCC
VIN = 0
−1.0
5.0
mA
+1.0
mA
pF
Clock Frequency, fSCLK
See Figure 2
400
kHz
Glitch Immunity, tSW
50
ns
Bus Free Time, tBUF
See Figure 2
1.3
ms
Start Setup Time, tSU;STA
See Figure 2
0.6
ms
Start Hold Time, tHD;STA
See Figure 2
0.6
ms
SCL Low Time, tLOW
See Figure 2
1.3
ms
SCL High Time, tHIGH
See Figure 2
0.6
ms
SCL, SDA Rise Time, tR
See Figure 2
300
ns
SCL, SDA Fall Time, tF
See Figure 2
300
ms
Data Setup Time, tSU;DAT
See Figure 2
100
ns
Detect Clock Low Timeout, tTIMEOUT
Can be optionally disabled
15
35
ms
1. All voltages are measured with respect to GND, unless otherwise specified. Logic inputs accept input high voltages up to VMAX even when
the device is operating below VMIN. Timing specifications are tested at logic levels of VIL = 0.8 V for a falling edge and at VIH = 2.0 V for a
rising edge.
2. Typicals are at TA = 25°C and represent the most likely parametric norm.
3. The delay is the time between the round robin finishing one set of measurements and starting the next.
4. Guaranteed by design; not production tested
SCL
tR
tLOW
tHD; STA
tHD; DAT
SDA
tBUF
P
S
tF
tHIGH
tSU; DAT
tHD; STA
tSU; STA
S
Figure 2. Serial Bus Timing Diagram
tSU; STO
P
http://onsemi.com
5

Share Link: 

datasheetq.com  [ Privacy Policy ]Request Datasheet ] [ Contact Us ]