ADT7485A データシートの表示（PDF） - Analog Devices

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ADT7485A

SST Digital Temperature Sensor and Voltage Monitor

Analog Devices 

ADT7485A

Parameter

SST TIMING

Bitwise Period, tBIT

High Level Time for Logic 1, tH12

High Level Time for Logic 0, tH02

Time to Assert SST High for Logic 1, tSU, HIGH

Hold Time, tHOLD3

Stop Time, tSTOP

Min

Typ

Max

Unit

0.495

500

μs

0.6 × tBIT

0.75 × tBIT 0.8 × tBIT

μs

0.2 × tBIT

0.25 × tBIT 0.4 × tBIT

μs

0.2 × tBIT

μs

0.5 × tBIT-M μs

1.25 × tBIT 2 × tBIT

2 × tBIT

μs

Time to Respond After a Reset, tRESET

Response Time to Speed Negotiation

After Power-Up

0.4

ms

500

μs

1 Guaranteed by design, not production tested.

2 Minimum and maximum bit times are relative to tBIT defined in the timing negotiation pulse.

3 Device is compatible with hold time specification as driven by SST originator.

Test Conditions/Comments

tBIT defined in speed negotiation

See SST Specification Rev 1.0

Device responding to a constant low

level driven by originator

Time after power-up when device can

participate in speed negotiation

Rev. 0 | Page 4 of 16

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