ADT7475 データシートの表示（PDF） - ON Semiconductor
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ADT7475 Datasheet PDF : 58 Pages
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ADT7475
ELECTRICAL CHARACTERISTICS TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted. (Note 1)
Parameter
Conditions
Min
Typ
Max
Unit
DIGITAL INPUT LOGIC LEVELS (THERM) ADTL+
Input High Voltage, VIH
Input Low Voltage, VIL
DIGITAL INPUT CURRENT
0.75 x VCC
V
0.8
V
Input High Current, IIH
Input Low Current, IIL
Input Capacitance, CIN
SERIAL BUS TIMING
VIN = VCC
VIN = 0 V
See Note 2 and Figure 2
±1
mA
±1
mA
5
pF
Clock Frequency, fSCLK
10
400
kHz
Glitch Immunity, tSW
50
ns
Bus Free Time, tBUF
4.7
ms
SCL Low Time, tLOW
4.7
ms
SCL High Time, tHIGH
4.0
50
ms
SCL, SDA Rise Time, tR
1000
ns
SCL, SDA Fall Time, tF
300
ms
Data Setup Time, tSU: DAT
250
ns
Detect Clock Low Timeout, tTIMEOUT
Can be optionally disabled
15
35
ms
1. All voltages are measured with respect to GND, unless otherwise specified. Typicals are at TA = 25°C and represent the most likely
parametric norm. Logic inputs accept input high voltages of up to VMAX, even when the device is operating down to VMIN. Timing
specifications are tested at logic levels of VIL = 0.8 V for a falling edge and VIH = 2.0 V for a rising edge.
2. SMBus timing specifications are guaranteed by design and are not production tested.
SCL
tLOW tR
tHD: STA
tHD: DAT
SDA
tBUF
P
S
tF
tHIGH
tSU: DAT
tHD: STA
tSU: STA
S
Figure 2. Serial Bus Timing Diagram
tSU: STO
P
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