ADT7476 データシートの表示（PDF） - ON Semiconductor
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ADT7476 Datasheet PDF : 68 Pages
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ADT7476
Table 4. ELECTRICAL CHARACTERISTICS (TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted.) (Note 1)
Parameter
Conditions
Min
Typ
Max
Unit
Digital Input Logic Levels (THERM) ADTL+
Input High Voltage, VIH
Input Low Voltage, VIL
Digital Input Current
Input High Current, IIH
Input Low Current, IIL
Input Capacitance, CIN
Serial Bus Timing (See Figure 2)
VIN = VCC
VIN = 0 V
0.75 x VCCP
−
−
−
−
V
0.8
V
−
±1
−
mA
−
±1
−
mA
−
5.0
−
pF
Clock Frequency, fSCLK
10
−
400
kHz
Glitch Immunity, tSW
−
−
50
ns
Bus Free Time, tBUF
4.7
−
−
ms
SCL Low Time, tLOW
4.7
−
−
ms
SCL High Time, tHIGH
4.0
−
50
ms
SCL, SDA Rise Time, tr
−
−
1,000
ns
SCL, SDA Fall Time, tf
−
−
300
ms
Data Setup Time, tSU;DAT
250
−
−
ns
Detect Clock Low Timeout, tTIMEOUT
Can be Optionally Disabled
15
−
35
ms
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. All voltages are measured with respect to GND, unless otherwise specified. Typical voltages are TA = 25°C and represent a parametric norm.
Logic inputs accept input high voltages up to VMAX, even when the device is operating down to VMIN. Timing specifications are tested at logic
levels of VIL = 0.8 V for a falling edge, and VIH = 2.0 V for a rising edge.
2. SMBus timing specifications are guaranteed by design and are not production tested.
SCL
SDA
tBUF
P
S
t LOW
tR
tHD; STA
tHD; DAT
tF
tHIGH
tSU; DAT
t HD; STA
tSU; STA
S
Figure 2. Serial Bus Timing Diagram
tSU; STO
P
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