ADUM1410 データシートの表示（PDF） - Analog Devices

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ADUM1410

Quad-Channel Digital Isolators

Analog Devices 

ADuM1410/ADuM1411/ADuM1412

Parameter

Symbol

Min

SWITCHING SPECIFICATIONS

ADuM141xARWZ

Minimum Pulse Width2

PW

Maximum Data Rate3

1

Propagation Delay4

tPHL, tPLH

20

Pulse Width Distortion, |tPLH − tPHL|4

PWD

Propagation Delay Skew5

tPSK

Channel-to-Channel Matching6

tPSKCD/OD

ADuM141xBRWZ

Minimum Pulse Width2

PW

Maximum Data Rate3

10

Propagation Delay4

tPHL, tPLH

20

Pulse Width Distortion, |tPLH − tPHL|4

PWD

Change vs. Temperature

Propagation Delay Skew5

tPSK

Channel-to-Channel Matching,

Codirectional Channels6

tPSKCD

Channel-to-Channel Matching,

Opposing-Directional Channels6

tPSKOD

All Models

Output Rise/Fall Time (10% to 90%) tR/tF

Common-Mode Transient Immunity |CMH|

25

at Logic High Output7

Common-Mode Transient Immunity |CML|

25

at Logic Low Output7

Refresh Rate

Input Enable Time8

Input Disable Time8

fr

tENABLE

tDISABLE

Input Dynamic Supply Current

per Channel9

IDDI (D)

Output Dynamic Supply Current

per Channel9

IDDO (D)

Typ Max Unit Test Conditions

1000 ns

CL = 15 pF, CMOS signal levels

Mbps CL = 15 pF, CMOS signal levels

75 100 ns

CL = 15 pF, CMOS signal levels

40

ns

CL = 15 pF, CMOS signal levels

50

ns

CL = 15 pF, CMOS signal levels

50

ns

CL = 15 pF, CMOS signal levels

100 ns

CL = 15 pF, CMOS signal levels

Mbps CL = 15 pF, CMOS signal levels

40 60

ns

CL = 15 pF, CMOS signal levels

5

ns

CL = 15 pF, CMOS signal levels

5

ps/°C CL = 15 pF, CMOS signal levels

30

ns

CL = 15 pF, CMOS signal levels

5

ns

CL = 15 pF, CMOS signal levels

6

ns

CL = 15 pF, CMOS signal levels

2.5

ns

CL = 15 pF, CMOS signal levels

35

kV/μs VIx = VDD1 or VDD2, VCM = 1000 V,

transient magnitude = 800 V

35

kV/μs VIx = 0 V, VCM = 1000 V,

transient magnitude = 800 V

1.1

Mbps

2.0

μs

VIA, VIB, VIC, VID = 0 V or VDD1

5.0

μs

VIA, VIB, VIC, VID = 0 V or VDD1

0.07

mA/

Mbps

0.02

mA/

Mbps

1 The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load

present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section.

See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through

Figure 15 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1410/ADuM1411/ADuM1412 channel configurations.

2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.

3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.

4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is

measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.

5 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load

within the recommended operating conditions.

6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of

the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with

inputs on opposing sides of the isolation barrier.

7 |CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. |CML| is the maximum common-mode voltage slew rate

that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient

magnitude is the range over which the common mode is slewed.

8 Input enable time is the duration from when VDISABLE is set low until the output states are guaranteed to match the input states in the absence of any input data logic

transitions. If an input data logic transition within a given channel does occur within this time interval, the output of that channel reaches the correct state within the

much shorter duration as determined by the propagation delay specifications within this data sheet. Input disable time is the duration from when VDISABLE is set high

until the output states are guaranteed to reach their programmed output levels, as determined by the CTRL2 logic state (see Table 14).

9 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information

on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current

for a given data rate.

Rev. H | Page 6 of 24

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