ADV7197KST データシートの表示（PDF） - Analog Devices
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ADV7197KST Datasheet PDF : 20 Pages
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ADV7197
3.3 V TIMING–SPECIFICATIONS (VAA = 3.15 V to 3.45 V, VREF = 1.235 V, RSET = 2470 ⍀, RLOAD = 300 ⍀. All specifications
TMIN to TMAX [0؇C to 70؇C] unless otherwise noted.)
Parameter
Min Typ Max Unit
Conditions
MPU PORT1
SCLOCK Frequency
10
SCLOCK High Pulsewidth, t1
0.6
SCLOCK Low Pulsewidth, t2
1.3
Hold Time (Start Condition), t3
0.6
Setup Time (Start Condition), t4
0.6
Data Setup Time, t5
100
SDATA, SCLOCK Rise Time, t6
SDATA, SCLOCK Fall Time, t7
Setup Time (Stop Condition), t8
0.6
RESET Low Time
100
400
kHz
µs
µs
µs
µs
ns
300
ns
300
ns
µs
ns
After This Period the 1st Clock Is Generated
Relevant for Repeated Start Condition
ANALOG OUTPUTS2
Analog Output Delay
Analog Output Skew
10
ns
0.5
ns
CLOCK CONTROL AND PIXEL PORT3
fCLK
tCLK
Clock High Time, t9
Clock Low Time, t10
Data Setup Time, t11
Data Hold Time, t12
Control Setup Time, t11
Control Hold Time, t12
Pipeline Delay
74.25 MHz
HDTV Mode
81
MHz
Async Timing Mode
5
1.5
ns
5
2.0
ns
2.0
ns
4.5
ns
7
ns
4.0
ns
16
Clock Cycles For 4:4:4 Pixel Input Format
NOTES
1Guaranteed by characterization.
2Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of DAC output full-scale transition.
3Data: Cb/Cr (9:0), Cr (9:0), Y (9:0); Control: HSYNC/SYNC, VSYNC/TSYNC; DV
Specifications subject to change without notice.
CLOCK
t9 t10
Y0
Y1
Y2
...
...
Yxxx
Yxxx
PIXEL INPUT
DATA
Cb0
Cr0
Cb1
Cr1
t12
t11
...
Cbxxx
Crxxx
Figure 1. 4:2:2 Input Data Format Timing Diagram
t9 – CLOCK HIGH TIME
t10 – CLOCK LOW TIME
t11 – DATA SETUP TIME
t12 – DATA HOLD TIME
REV. 0
–5–
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