HSYNC
VSYNC
A
DV
PIXEL
DATA
B
AMIN = 44 CLK CYCLES FOR 1080i
AMIN = 70 CLK CYCLES FOR 720P
BMIN = 236 CLK CYCLES FOR 1080i
BMIN = 300 CLK CYCLES FOR 720P
Figure 4. Input Timing Diagram
ADV7197
Y Y YY
Cr Cr Cr Cr
Cb Cb Cb Cb
t3
SDA
t5
t3
t6
t1
SCL
t2
t7
t4
t8
Figure 5. MPU Port Timing Diagram
REV. 0
–7–