ADXL313 データシートの表示（PDF） - Analog Devices

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ADXL313

Digital Accelerometer / 32-Lead Lead Frame Chip

Analog Devices 

ADXL313

SERIAL COMMUNICATIONS

I2C and SPI digital communications are available. In both cases,

the ADXL313 operates as a slave. I2C mode is enabled if the CS pin

is tied high to VDD I/O. The CS pin must always be tied high to

VDD I/O or be driven by an external controller because there is no

default mode if the CS pin is left unconnected. Therefore, not

taking these precautions may result in an inability to communicate

with the part. In SPI mode, the CS pin is controlled by the bus

master. In both SPI and I2C modes of operation, ignore data

transmitted from the ADXL313 to the master device during

writes to the ADXL313.

SPI

For SPI communication, either 3- or 4-wire configuration is

possible, as shown in the connection diagrams in Figure 15 and

Figure 16. Clearing the SPI bit in the DATA_FORMAT register

(Address 0x31) selects 4-wire mode, whereas setting the SPI bit

selects 3-wire mode. The maximum SPI clock speed is 5 MHz

with 100 pF maximum loading, and the timing scheme follows

clock polarity (CPOL) = 1 and clock phase (CPHA) = 1. If power

is applied to the ADXL313 before the clock polarity and phase

of the host processor are configured, the CS pin must be brought

high before changing the clock polarity and phase. When using

the 3-wire SPI configuration, it is recommended that the SDO

pin be either pulled up to VDD I/O or pulled down to GND via a

10 kΩ resistor.

ADXL313

CS

SDIO

SDO

SCLK

PROCESSOR

D OUT

D IN/OUT

D OUT

Figure 15. 3-Wire SPI Connection Diagram

ADXL313

CS

SDI

SDIO

SCLK

PROCESSOR

D OUT

D OUT

D IN

D OUT

Figure 16. 4-Wire SPI Connection Diagram

Data Sheet

CS is the serial port enable line and is controlled by the SPI master.

This line must go low at the start of a transmission and high at

the end of a transmission, as shown in Figure 17 to Figure 19.

SCLK is the serial port clock and is supplied by the SPI master.

SCLK idles high during a period of no transmission. SDI and

SDO are the serial data input and output, respectively. Data is

updated on the falling edge of SCLK and sampled on the rising

edge of SCLK.

To read or write multiple bytes in a single transmission, the

multiple-byte bit, located after the R/W bit in the first byte transfer

(MB in Figure 17 to Figure 19), must be set. After the register

addressing and the first byte of data, each subsequent set of

clock pulses (eight clock pulses) causes the ADXL313 to point

to the next register for a read or write. This shifting continues

until the clock pulses cease and CS is deasserted. To perform reads

or writes on different, nonsequential registers, CS must be

deasserted between transmissions, and the new register must be

addressed separately.

The timing diagram for 3-wire SPI reads or writes is shown in

Figure 17. The 4-wire equivalents for SPI reads and writes are

shown in Figure 18 and Figure 19, respectively. For correct

operation of the part, the logic thresholds and timing parameters

in Table 8 and Table 9 must be met at all times.

Use of the 3200 Hz and 1600 Hz output data rates is recommended

only with SPI communication rates greater than or equal to 2

MHz. The 800 Hz output data rate is recommended only for

communication speeds greater than or equal to 400 kHz, and

the remaining data rates scale proportionally. For example, the

minimum recommended communication speed for a 200 Hz

output data rate is 100 kHz. Operation at an output data rate

below the recommended minimum may result in undesirable

effects on the acceleration data, including missing samples or

additional noise.

Rev. 0 | Page 10 of 28

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