AIC1573CS データシートの表示（PDF） - Analog Intergrations

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AIC1573CS

5-bit DAC, Synchronous PWM Power Regulator with Simple PWM Power Regulator, LDO And Linear Controller

Analog Intergrations 

AIC1573

nect the PHASE1 pin to source

of the external high-side N-

MOSFET. This pin detects the

voltage drop across the high-side

N-MOSFET RDS(ON) for over-

current protection.

Pin 27: UGATE1:External high-side N-MOSFET

gate drive pin. Connect UGATE1

to the synchronous PWM con-

Pin 28: VCC:

verter’s gate of the external high-

side N-MOSFET .

The chip power supply pin. It also

provides the gate bias charge for

all the MOSFETs controlled by

the IC. Recommended supply

voltage is 12V. The voltage at this

pin is monitored for Power-On-

Reset purpose.

n APPLICATIONS INFORMATION

The AIC1573 is designed for microprocessor com-

puter applications with 3.3V and 5V power, and

12V bias input. This IC has two PWM controller

and two linear controllers. The first PWM (PWM1)

controller is designed to regulate the microproces-

sor core voltage (VOUT1) by driving 2 MOSFETs

(Q1 and Q2) in a synchronous rectified buck con-

verter configuration. The core voltage is regulated to

a level programmed by the 5 bit D/A converter. The

second PWM (PWM2) controller is designed to

regulate the advanced graphics port (AGP) bus

voltage (VOUT2). PWM2 One of the linear control-

lers is designed to regulate the advanced graphic

port (AGP) bus voltage (VOUT2). PWM2 controller

drives a MOSFET (Q3) in a standard buck converter

and regulates the output voltage to a digitally-

programmable level of 1.5V or 3.3V.Selection of

either output voltage is achieved by applying the

proper logic level at the SELECT pin. The two linear

controllers supply the 1.5V GTL bus power (VOUT3)

and 1.8V memory power (VOUT4).

The Power-On-Reset (POR) function continually

monitors the input supply voltage +12V at VCC pin,

the 5V input voltage at OCSET pin, and the 3.3V

input at VAUX pin. The POR function initiates soft-

start operation after all three input supply voltage

exceeds their POR thresholds.

Soft-Start

The POR function initiates the soft-start sequence.

An internal 25µA current source charges an exter-

nal capacitor (CSS) on the SS pin to 4.5V. The

PWM error amplifier reference input (Non-inverting

terminal) and output (COMP1 pin) is clamped to a

level proportional to the SS pin voltage. As the SS

pin voltage slew from 1V to 4V, the output clamp

generates PHASE pulses of increasing width that

charge the output capacitors. After the output volt-

age increases to approximately 70% of the set

value, the reference-input clamp slows the output

voltage rate-of-rise and provides a smooth transition

to the final set voltage. Additionally, all linear regu-

lator’s reference inputs are clamped to a voltage

proportional to the SS pin voltage. This method

provides a rapid and controlled output voltage rise.

Fig.1 and Fig.2 show the soft-start sequence for the

typical application. The internal oscillator’s triangu-

lar waveform is compared to the clamped error am-

plifier output voltage. As the SS pin voltage in-

creases, the pulse width on PHASE pin increases.

The interval of increasing pulse width continues un-

til output reaches sufficient voltage to transfer con-

trol to the input reference clamp.

12

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