AIC1573CS データシートの表示（PDF） - Analog Intergrations

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AIC1573CS

5-bit DAC, Synchronous PWM Power Regulator with Simple PWM Power Regulator, LDO And Linear Controller

Analog Intergrations 

AIC1573



− 10 log1−





F

FLC

 2









2

+



F

FLC ×

Q



2







where

FLC =

1

;

2π LOCO

FESR

=

2π

1

× RESR

× CO

;

1=

Q

CO

LO

× R ESR

+

LO × 1

CO RLOAD

The break frequency of Internal Compensation Gain

are given by

FZ1 = 2.6KHz ;

FZ 2 = 24KHz ;

FP1 = 30KHz ;

FP2 = 400KHz

n PHYSICAL DIMENSIONS

60

FZ1 FZ2 FP1

40

Compensation Gain

20

FP2

20log(VIN/δVOSC)

0

FOdB

Modulation

Gain

-20

100

FLC

F

1k

FESR

10k

Closed Loop

Gain

100k

1M

10M

Frequency (KHz)

Fig. 21 Bode Plot of Converter Gain

Bode Plot of Converter Gain

Sampling theory shows that F0dB must be less that

half the switching frequency for the loop stables.

But it must be considerably less than that, or there

will be large amplitude switching frequency ripple at

the output. Thus, the usual practices is to fix F0dB

at 1/4 to 1/5 the switching frequency.

l 28 LEAD PLASTIC SO (unit: mm)

D

E

H

e

B

A

C

L

SYMBOL

A

A1

B

C

D

E

e

H

L

MIN

MAX

2.35

2.65

0.10

0.30

0.33

0.51

0.23

0.32

17.70

18.10

7.40

7.60

1.27 (TYP)

10.00

10.65

0.40

1.27

19

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