MITSUBISHI 〈DIGITAL ASSP〉
M66221SP/FP
256 × 9-BIT MAIL-BOX
Contention Read Cycle (WE = VIH, OE = VIL)
Contention read cycle No .1 (Address control) See Notes 10 and 11.
Address A
(Address B)
∗ Address matching
tAPS
Address B
(Address A)
Not Ready B
(Not Ready A)
∗
tNAA
I/O0B~I/O8B
(I/O0A~I/O8A)
tv(A)
Previous cycle data
∗ Address A = Address B
Address not matching
tNDA
tNO
Data output
determined
ta(A)
Contention read cycle No. 2 (CS control) See Notes 10 and 12.
Addresses
A&B
∗ Address matching
CSA
(CSB)
CSB
(CSA)
Not Ready B
(Not Ready A)
I/O0B~I/O8B
(I/O0A~I/O8A)
tAPS
tNAC
tNDC
ten(CS)
tNO
ta(CS)
∗ Address A = Address B
Notes 10: The Not Ready output of the first-in port holds “H”.
11: When CS is set to “L” before the address input is determined.
12: When the address input is determined before CS transition to “L”.
Data output determined
9