ASAHI KASEI
[AK5384]
PIN/FUNCTION
No. Pin Name
1 LIN2+
2 LIN2−
3 RIN2+
4 RIN2−
5 TEST
6 VCOM
7 AVSS
8 AVDD
9 DIF
10 TDM1
11 TDM0
12 TDMIN
13 MCLK
14 OVF
15 LRCK
16 BICK
17 SDTO2
18 SDTO1
19 TVDD
20 DVDD
21 DVSS
22 PDN
23 CKS
24 M/S
25 RIN1−
26 RIN1+
27 LIN1−
28 LIN1+
I/O Function
I ADC2 Lch Positive Analog Input Pin
I ADC2 Lch Negative Analog Input Pin
I ADC2 Rch Positive Analog Input Pin
I ADC2 Rch Negative Analog Input Pin
I Test Pin (Connected to AVSS)
Common Voltage Output Pin, AVDD/2
O
Normally connected to AVSS with a 0.1µF ceramic capacitor in parallel with an
electrolytic capacitor less than 2.2µF.
- Analog Ground Pin
- Analog Power Supply Pin, 4.75 ∼ 5.25V
I
Audio Interface Format Pin
“L” : 24bit MSB justified, “H” : 24bit I2S Compatible
I
TDM I/F BICK Frequency Select Pin
“L” : 256fs, “H” : 128fs
I
TDM I/F Format Enable Pin
“L” : Normal Mode, “H” : TDM Mode
I TDM Data Input Pin
I Master Clock Input Pin
O
Analog Input Overflow Detect Pin
This pin goes to “H” if one of four analog inputs overflows.
I/O
Output Channel Clock Pin
“L” Output in Master Mode at Power-down mode.
I/O
Audio Serial Data Clock Pin
“L” Output in Master Mode at Power-down mode.
O
ADC2 Audio Serial Data Output Pin
“L” Output at Power-down mode.
O
ADC1 Audio Serial Data Output Pin
“L” Output at Power-down mode.
- Output Buffer Power Supply Pin, 3.0 ∼ 5.25V
- Digital Power Supply Pin, 4.75 ∼ 5.25V
- Digital Ground Pin
Power-Down Mode Pin
I
When “L”, the circuit is in power-down mode.
The AK5384 should always be reset upon power-up.
Master Clock Select Pin
I
“L” : 256fs, “H” : 512fs
This pin is enabled in Master Mode.
I
Master / Slave Mode Pin
“L” : Slave Mode, “H” : Master Mode
I ADC1 Rch Negative Analog Input Pin
I ADC1 Rch Positive Analog Input Pin
I ADC1 Lch Negative Analog Input Pin
I ADC1 Lch Positive Analog Input Pin
Note: All digital input pins should not be left floating.
MS0225-E-00
-3-
2003/05