AKD4552-A データシートの表示（PDF） - Asahi Kasei Microdevices
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AKD4552-A Datasheet PDF : 33 Pages
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ASAHI KASEI
[AKD4552-A]
(5) Evaluation of A/D using D/A converted data
It is possible to make evaluation in the form of analog inputs and analog outputs by interfacing with various
AKM’s D/A evaluation boards with PORT3 (ROM). Nothing should be connected to PORT1 (DIR).
JP3
LRCK
JP4
BCLK
JP6
SDTI
JP8
JP13
XTE
EXT
ADC DIR ADC DIR ADC DIR
• Clock example
5-1) Normal speed of ADC (MCLK=256fs)
Do not use X2.
JP2
MCKO
M1 M2
JP7
SPEED
X4
X2
X1
JP9
MCLK
X1
X2
JP10
BCFS
X1
X4
JP11
CLK
JP12
LRFS
DIR
EXT X1
X4
XTL
5-2) Normal speed of ADC (MCLK=512fs)
Do not use X2.
JP2
MCKO
M1 M2
JP7
SPEED
X4
X2
X1
JP9
MCLK
X1
X2
JP10
BCFS
X1
X4
JP11
CLK
JP12
LRFS
DIR
EXT X1
X4
XTL
<KM080600>
-7-
2005/10
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