PDM41256SA10TI データシートの表示（PDF） - Paradigm Technology
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PDM41256SA10TI Datasheet PDF : 8 Pages
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Features
n High-speed access times
Com’l: 7, 8, 10, 12 and 15ns
Ind’l: 8, 10, 12 and 15ns
(use 15ns for slower designs)
n Low power operation (typical)
- PDM41256SA
Active: 475 mW
Standby: 100 mW
- PDM41256LA
Active: 425mW
Standby: 25 mW
n Single +5V (±10%) power supply
n TTL-compatible inputs and outputs
n Packages
Plastic SOJ (300 mil) - SO
Plastic TSOP (I) - T
PDM41256
256K Static RAM
32K x 8-Bit
1
Description
2 The PDM41256 is a high-performance CMOS static
RAM organized as 32,768 x 8 bits. Writing to this
device is accomplished when the write enable (WE)
and the chip enable (CE) inputs are both LOW.
Reading is accomplished when WE remains HIGH
and CE and OE are both LOW.
3
The PDM41256 operates from a single +5V power
supply and all the inputs and outputs are fully TTL-
4 compatible. The PDM41256 comes in two versions:
the standard power version PDM41256SA and the
low power version PDM41256LA. Both versions are
functionally the same and differ only in their power
consumption.
5
The PDM41256 is available in a 28-pin plastic TSOP
(I) and a 28-pin 300-mil plastic SOJ.
6
Functional Block Diagram
A
•
0
•
Addresses •
•
•
A 14
I/O 0
•
•
I/O 7
CE
WE
OE
Decoder
Input
Data
Control
• Memory
•
•
•
Matrix
•
•
•••••
Column I/O
•
•
•
7
8
9
10
11
12
Rev. 4.4 - 4/29/98
1
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