PDM41256SA10TI データシートの表示（PDF） - Paradigm Technology
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PDM41256SA10TI Datasheet PDF : 8 Pages
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Write Cycle No. 1 (Write Enable Controlled)
t WC
ADDR
t AW
t CW
t AH
CE
t AS
WE
t WP
DIN
DOUT
t HZWE
t DS
t DH
DATA VALID
HIGH Z
t LZWE
Write Cycle No. 2 (Chip Enable Controlled)
ADDR
CE
t WC
t AW
tAS
tCW
t AH
t WP
WE
t DS
t DH
DIN
DATA VALID
PDM41256
UNDEFINED
DON'T CARE
AC Electrical Characteristics
Description
-7(6)
-8(6)
-10(6)
-12
-15
WRITE Cycle
Sym Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
WRITE cycle time
Chip enable to end of write
Address valid to end of write
Address setup time
Address hold from end of write
Write pulse width
Data setup time
Data hold time
Write disable to output in low Z(4, 5)
Write enable to output in high Z(4, 5)
tWC
7
tCW
7
tAW
7
tAS
0
tAH
0
tWP
7
tDS
6
tDH
0
tLZWE 0
tHZWE
8
8
8
0
0
8
7
0
0
3
10
12
15
ns
10
10
12
ns
10
10
12
ns
0
0
0
ns
0
0
0
ns
8
8
11
ns
7
7
7
ns
0
0
0
ns
0
0
0
ns
3
3
3
3 ns
SHADED AREA = PRELIMINARY DATA
6
Rev. 4.4 - 4/29/98
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