IS61SF51218T データシートの表示（PDF） - Integrated Silicon Solution
部品番号
コンポーネント説明
メーカー
IS61SF51218T
Integrated Silicon Solution
IS61SF51218T Datasheet PDF : 21 Pages
| |||
IS61SF25632T/D IS61LF25632T/D
IS61SF25636T/D IS61LF25636T/D
IS61SF51218T/D IS61LF51218T/D
ISSI®
256K x 32, 256K x 36, 512K x 18
SYNCHRONOUS FLOW-THROUGH
STATIC RAM
PRELIMINARY INFORMATION
NOVEMBER 2000
FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Pentium™ or linear burst sequence control using
MODE input
• Three chip enable option for simple depth expansion
and address pipelining
• Common data inputs and data outputs
• JEDEC 100-Pin TQFP and
119-pin PBGA package
• Single +3.3V, +10%, –5% power supply
• Power-down snooze mode
• 3.3V I/O for SF
• 2.5V I/O for LF
• Snooze MODE for reduced-power standby
• T version (three chip selects)
• D version (two chip selects)
FAST ACCESS TIME
Symbol
Parameter
-8*
tKQ
Clock Access Time
8
tKC
Cycle Time
10
Frequency
100
*This speed available only in SF version
DESCRIPTION
The ISSI IS61SF25632, IS61SF25636, IS61SF51218,
IS61LF25632, IS61LF25636, and IS61LF51218 are high-speed,
low-power synchronous static RAMs designed to provide
a burstable, high-performance, secondary cache for the
Pentium™, 680X0™, and PowerPC™ microprocessors.
The IS61SF25632 and IS61LF25632 are organized as
262,144 words by 32 bits and the IS61SF25636 and
IS61LF25636 are organized as 262,144 words by 36 bits.
The IS61SF51218 and IS61LF51218 are organized as
524,288 words by 18 bits. Fabricated with ISSI's advanced
CMOS technology, the device integrates a 2-bit burst
counter, high-speed SRAM core, and high-drive capability
outputs into a single monolithic circuit. All synchronous
inputs pass through registers that are controlled by a
positive-edge-triggered single clock input.
Write cycles are internally self-timed and are initiated by the
rising edge of the clock input. Write cycles can be from one
to four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
Byte write operation is performed by using byte write
enable (BWE).input combined with one or more individual
byte write signals (BWx). In addition, Global Write (GW)
is available for writing all bytes at one time, regardless of
the byte write controls.
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller)
input pins. Subsequent burst addresses can be generated
internally and controlled by the ADV (burst address
advance) input pin.
The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW. Interleave
burst is achieved when this pin is tied HIGH or left floating.
-8.5
-9
-10
Units
8.5
9
10
ns
11
15
15
ns
90
66
66
MHz
This document contains PRELIMINARY INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the
best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
1
PRELIMINARY INFORMATION Rev. 00A
04/17/01
Share Link: