HYB514256B データシートの表示（PDF） - Infineon Technologies
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HYB514256B Datasheet PDF : 22 Pages
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256 K × 4-Bit Dynamic RAM
Low Power 256 K × 4-Bit Dynamic RAM
HYB 514256B/BJ-50/-60/-70
HYB 514256BL/BJL-50/-60/-70
Advanced Information
• 262 144 words by 4-bit organization
• Fast access and cycle time
50 ns access time
95 ns cycle time (-50 version)
60 ns access time
110 ns cycle time (-60 version)
70 ns access time
130 ns cycle time (-70 version)
• Fast page mode cycle time
35 ns (-50 version)
40 ns (-60 version)
45 ns (-70 version)
• Low power dissipation
max. 495 mW active (-50 version)
max. 440 mW active (-60 version)
max. 385 mW active (-70 version)
max. 5.5 mW standby
max. 1.1 mW standby for L-version
Ordering Information
Type
HYB 514256B-50
HYB 514256B-60
HYB 514256B-70
HYB 514256BJ-50
HYB 514256BJ-60
HYB 514256BJ-70
HYB 514256BL-50
HYB 514256BL-60
HYB 514256BL-70
HYB 514256BJL-50
HYB 514256BJL-60
HYB 514256BJL-70
Ordering Code
Q67100-Q1044
Q67100-Q530
Q67100-Q433
Q67100-Q1054
Q67100-Q536
Q67100-Q537
on request
Q67100-Q542
Q67100-Q543
on request
Q67100-Q608
Q67100-Q607
• Single + 5 V (± 10 %) supply with a built-in VBB
generator
• Output unlatched at cycle end allows two-
dimensional chip selection
• Read-modify-write, CAS-before-RAS
refresh, RAS-only refresh, hidden-refresh
and fast page mode capability
• All inputs, outputs and clocks
TTL-compatible
• 512 refresh cycles/8 ms
512 refresh cycles/64 ms
for L-version only
• Plastic Packages: P-DIP-20-2,
P-SOJ-26/20-1
Package
P-DIP-20-2
P-DIP-20-2
P-DIP-20-2
P-SOJ-26/20-1
P-SOJ-26/20-1
P-SOJ-26/20-1
P-DIP-20-2
P-DIP-20-2
P-DIP-20-2
P-SOJ-26/20-1
P-SOJ-26/20-1
P-SOJ-26/20-1
Description
DRAM (access time 50ns)
DRAM (access time 60 ns)
DRAM (access time 70 ns)
DRAM (access time 50 ns)
DRAM (access time 60 ns)
DRAM (access time 70 ns)
DRAM (access time 50 ns)
DRAM (access time 60 ns)
DRAM (access time 70 ns)
DRAM (access time 50 ns)
DRAM (access time 60 ns)
DRAM (access time 70 ns)
Semiconductor Group
55
01.95
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