EDS1232CABB データシートの表示（PDF） - Elpida Memory, Inc

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EDS1232CABB

128M bits SDRAM

Elpida Memory, Inc 

EDS1232CABB, EDS1232CATA

Pin Capacitance (TA = 25°C, f = 1MHz)

Parameter

Input capacitance

Data input/output

capacitance

90-ball FBGA

Symbol Pins

min. Typ

CI1 Address

1.5

—

CI2

CLK, CKE, /CS, /RAS,

/CAS, /WE, DQM

1.5

—

CI/O DQ

3.0

—

max.

3.0

3.0

86-pin TSOP (II)

min. Typ max.

2.5

—

4.0

2.5

—

4.0

Unit Notes

pF

pF

5.5

4.0

—

6.5

pF

AC Characteristics (TA = 0 to +70°C, VDD, VDDQ = 2.5V±0.2V, VSS, VSSQ = 0V)

-75

-1A

Parameter

System clock cycle time

(CL = 2)

(CL = 3)

CLK high pulse width

CLK low pulse width

Access time from CLK

Data-out hold time

CLK to Data-out low impedance

CLK to Data-out high impedance

Input setup time

Input hold time

CKE setup time (Power down exit)

ACT to REF/ACT command period

(operation)

(refresh)

Active to Precharge command period

Active command to column command

(same bank)

Precharge to active command period

Write recovery or data-in to precharge

lead time

Last data into active latency

Symbol

tCK

tCK

tCH

tCL

tAC

tOH

tLZ

tHZ

tSI

tHI

tCKSP

tRC

tRC

tRAS

tRCD

tRP

tDPL

tDAL

Active (a) to Active (b) command period tRRD

Mode register set cycle time

tRSC

Transition time (rise and fall)

Refresh period

(4096 refresh cycles)

tT

tREF

min.

max.

min.

max.

Unit

Notes

10

—

10

—

ns

7.5

—

10

—

ns

2.5

—

3

—

ns

2.5

—

3

—

ns

—

5.4

—

6

ns

2

—

2

—

ns

0

—

0

—

ns

2

5.4

2

6

ns

1.5

—

2

—

ns

0.8

—

1

—

ns

1.5

—

2

—

ns

67.5



70



ns

67.5



70

45

120000

50



ns

120000

ns

20



20



ns

20



20



ns

15



20



ns

2CLK +

20ns



2CLK +

20ns

—

15



20

—

ns

2



2



CLK

0.5

30

0.5

30

ns

—

64

—

64

ms

Preliminary Data Sheet E0247E40 (Ver. 4.0)

7

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