EDS1232CABB データシートの表示（PDF） - Elpida Memory, Inc
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EDS1232CABB Datasheet PDF : 55 Pages
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EDS1232CABB, EDS1232CATA
Relationship Between Frequency and Minimum Latency
Parameter
-75
-1A
Frequency (MHz)
133
100
100
77
tCK (ns)
Symbol
7.5
10
10
13
Active command to column command
(same bank)
lRCD
3
2
2
2
Active command to active command
(same bank)
lRC
9
7
7
6
Active command to precharge command
(same bank)
lRAS
6
5
5
4
Precharge command to active command
(same bank)
lRP
3
2
2
2
Write recovery or data-in to precharge
command (same bank)
lDPL
2
2
2
2
Active command to active command
(different bank)
lRRD
2
2
2
2
Self refresh exit time
lSREX
1
1
1
1
Last data in to active command
(Auto precharge, same bank)
lDAL
5
4
4
4
Self refresh exit to command input
lSEC
9
7
7
6
Precharge command to high impedance
(CL = 2)
lHZP
2
2
2
(CL = 3)
Last data out to active command
(auto precharge) (same bank)
Last data out to precharge
(early precharge)
(CL = 2)
(CL = 3)
lHZP
3
3
3
3
lAPR
1
1
1
1
lEP
–1
–1
–1
lEP
–2
–2
–2
–2
Column command to column command
lCCD
1
1
1
1
Write command to data in latency
lWCD
0
0
0
0
DQM to data in
lDID
0
0
0
0
DQM to data out
lDOD
2
2
2
2
CKE to CLK disable
lCLE
1
1
1
1
Register set to active command
lMRD
2
2
2
2
/CS to command disable
lCDD
0
0
0
0
Power down exit to command input
lPEC
1
1
1
1
Notes: 1. IRCD to IRRD are recommended value.
2. Be valid [DESL] or [NOP] at next command of self refresh exit.
3. Except [DESL] and [NOP]
Notes
1
1
1
1
1
1
2
= [lDPL + lRP]
= [lRC]
3
Preliminary Data Sheet E0247E40 (Ver. 4.0)
9
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