AM29LV200BT-50RSE データシートの表示（PDF） - Advanced Micro Devices

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AM29LV200BT-50RSE

2 Megabit (256 K x 8-Bit/128 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory

Advanced Micro Devices 

DATA SHEET

DEVICE BUS OPERATIONS

This section describes the requirements and use of the

device bus operations, which are initiated through the

internal command register. The command register

itself does not occupy any addressable memory loca-

tion. The register is composed of latches that store the

commands, along with the address and data informa-

tion needed to execute the command. The contents of

the register serve as inputs to the internal state

machine. The state machine outputs dictate the func-

tion of the device. Table 1 lists the device bus

operations, the inputs and control levels they require,

and the resulting output. The following subsections

describe each of these operations in further detail.

Table 1. Am29LV200B Device Bus Operations

Read

Write

Operation

Standby

Output Disable

Reset

Sector Protect (Note 2)

Sector Unprotect (Note 2)

Temporary Sector

Unprotect

CE# OE# WE# RESET#

Addresses

(Note 1)

L

LH

H

AIN

L HL

H

AIN

VCC ±

0.3 V

X

X

VCC ±

0.3 V

X

L HH

H

X

X XX

L

X

L HL

VID

Sector Address, A6 = L,

A1 = H, A0 = L

L HL

VID

Sector Address, A6 = H,

A1 = H, A0 = L

DQ0–

DQ7

DOUT

DIN

High-Z

High-Z

High-Z

DIN

DIN

DQ8–DQ15

BYTE#

BYTE#

= VIH

= VIL

DOUT DQ8–DQ14 = High-Z,

DIN

DQ15 = A-1

High-Z

High-Z

High-Z

High-Z

High-Z

High-Z

X

X

X

X

X XX

VID

AIN

DIN

DIN

High-Z

Legend:

L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, AIN = Addresses In, DIN = Data In, DOUT = Data Out

Notes:

1. Addresses are A16:A0 in word mode (BYTE# = VIH), A16:A-1 in byte mode (BYTE# = VIL).

2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector

Protection/Unprotection” section.

Word/Byte Configuration

The BYTE# pin controls whether the device data I/O

pins DQ15–DQ0 operate in the byte or word configura-

tion. If the BYTE# pin is set at logic ‘1’, the device is in

word configuration, DQ15–DQ0 are active and con-

trolled by CE# and OE#.

If the BYTE# pin is set at logic ‘0’, the device is in byte

configuration, and only data I/O pins DQ0–DQ7 are

active and controlled by CE# and OE#. The data I/O

pins DQ8–DQ14 are tri-stated, and the DQ15 pin is

used as an input for the LSB (A-1) address function.

Requirements for Reading Array Data

To read array data from the outputs, the system must

drive the CE# and OE# pins to VIL. CE# is the power

control and selects the device. OE# is the output

control and gates array data to the output pins. WE#

should remain at VIH. The BYTE# pin determines

whether the device outputs array data in words or

bytes.

The internal state machine is set for reading array data

upon device power-up, or after a hardware reset. This

ensures that no spurious alteration of the memory

content occurs during the power transition. No

command is necessary in this mode to obtain array

data. Standard microprocessor read cycles that assert

valid addresses on the device address inputs produce

valid data on the device data outputs. The device

remains enabled for read access until the command

register contents are altered.

See “Reading Array Data” for more information. Refer

to the AC Read Operations table for timing specifica-

tions and to Figure 13 for the timing diagram. ICC1 in the

DC Characteristics table represents the active current

specification for reading array data.

Writing Commands/Command Sequences

To write a command or command sequence (which

includes programming data to the device and erasing

October 10, 2006 21521D6

Am29LV200B

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