AM7990 データシートの表示（PDF） - Advanced Micro Devices

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AM7990

Serial Interface Adapter (SIA)

Advanced Micro Devices 

PIN DESCRIPTION

CLSN

Collision (Output, TTL Active HIGH)

Signals at the Collision± terminals meeting threshold

and pulse-width requirements will produce a logic

HIGH at CLSN output. When no signal is present at

Collision±, CLSN output will be LOW.

RX

Receive Data (Output)

A MOS/TTL output, recovered data. When there is no

signal at Receive± and TEST is HIGH, RX is HIGH. RX

is actuated with RCLK and remains active until RENA

is deasserted at the end of the message. During recep-

tion, RX is synchronous with RCLK and changes after

the rising edge of RCLK. When TEST is LOW, RX is

enabled.

RENA

Receive Enable (Output, TTL Active HIGH)

When there is no signal at Receive+, RENA is LOW.

Signals meeting threshold and pulse-width “on” re-

quirements will produce a logic HIGH at RENA. When

RENA is HIGH, Receive+ signals meeting threshold

and pulse-width “off” requirements will produce a LOW

at RENA.

RCLK

Receive Clock (Output)

A MOS/TTL output, recovered clock. When there is no

signal at Receive± and TEST is HIGH, RCLK is LOW.

RCLK is activated 1/4 bit time after the second negative

Manchester preamble clock transition at Receive± and

remains active until after an end of message. When

TEST is LOW, RCLK is enabled and meets minimum

pulse-width specifications.

TX

Transmit (Input)

TTL-compatible input. When TENA is HIGH, signals at

TX meeting setup and hold time to TCLK will be

encoded as normal Manchester at Transmit+ and

Transmit–.

s TX HIGH: Transmit+ is negative with respect to

Transmit– for first half of data bit cell.

s TX LOW: Transmit+ is positive with respect to

Transmit– for first half of data bit cell.

TENA

Transmit Enable (Input)

TTL-compatible input. Active HIGH data encoder

enable. Signals meeting setup and hold time to TCLK

will allow encoding of Manchester data from TX to

Transmit+ and Transmit–.

TCLK

Transmit Clock (Output)

MOS/TTL output. TCLK provides symmetrical HIGH

and LOW clock signals at data rate for reference timing

of data to be encoded. It also provides clock signals for

the controller chip (Am7990—LANCE) and an internal

timing reference for receive path voltage-controlled

oscillators.

Transmit+, Transmit–

Transmit (Outputs)

A differential line output. This line pair is intended to op-

erate into terminated transmission lines. For signals

meeting setup and hold time to TCLK at TENA and TX,

Manchester clock and data are outputted at Transmit+/

Transmit–. When operating into a 78 Ω terminated

transmission line, signaling meets the required output

levels and skew for both Ethernet and IEEE 802.3 drop

cables.

Receive+, Receive–

Receiver (Inputs)

A differential input. A pair of internally biased line re-

ceivers consisting of a carrier detect receiver with offset

threshold and noise filtering to detect the line activity,

and a data recovery receiver with no offset for

Manchester data decoding.

Collision+, Collision–

Collision (Inputs)

A differential input. An internally biased line receiver

input with offset threshold and noise filtering. Signals at

Collision± have no effect on data-path functions.

TSEL

Transmit Mode Select (Output, Open Collector;

Input, Sense Amplifier)

s TSEL LOW: Idle transmit state Transmit+ is positive

with respect to Transmit–.

s TSEL HIGH: Idle transmit state Transmit+ and

Transmit– are equal, providing “zero” differential to

operate transformer-coupled loads.

When connected with an RC network, TSEL is held

LOW during transmission. At the end of transmission

the open collector output is disabled, allowing TSEL to

rise and provide a smooth transmission from logic

HIGH to “zero” differential idle. Delay and output return

to zero are externally controlled by the RC network at

TSEL and Transmit± load inductance.

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Am7992B

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