M5M5255DP-45LL データシートの表示（PDF） - MITSUBISHI ELECTRIC
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M5M5255DP-45LL Datasheet PDF : 7 Pages
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'97.4.7
MITSUBISHI LSIs
M5M5255DP,FP -45LL,-55LL,-70LL,
-45XL,-55XL,-70XL
262,144-BIT (32,768-WORD BY 8-BIT) CMOS STATIC RAM
FUNCTION
The operation mode of the M5M5255DP,FP is determined
by a combination of the device control inputs /S1, S2 and
/W. Each mode is summarized in the function table.
A write cycle is executed whenever the low level /W
overlaps with the low level /S1 and the high level S2. The
address must be set up before the write cycle and must be
stable during the entire cycle. The data is latched into a cell
on the trailing edge of /W, /S1 or S2, whichever occurs first,
requiring the set-up and hold time relative to these edge to
be maintained.
A read cycle is executed by setting /W at a high level
while /S1 and S2 are in an active state(/S1="L", S2="H").
When setting /S1 at a high level or S2 at a low level, the
chip is in a non-selectable mode in which both reading and
writing are disabled. In this mode, the output stage is in a
high-impedance state, allowing OR-tie with other chips and
memory expansion by /S1 and S2. The power supply
current is reduced as low as the stand-by current which is
specified as Icc3 or Icc4, and the memory data can be held
at +2V power supply, enabling battery back-up operation
during power failure or power-down operation in the
non-selected mode.
FUNCTION TABLE
/S1 S2 /W
H XX
LLX
L HL
L HH
Mode
Non selection
Non selection
Write
Read
DQ
High-impedance
High-impedance
DIN
DOUT
Icc
Stand-by
Stand-by
Active
Active
FUNCTION TABLE
ADDRESS
INPUT
A 8 25
A 13 26
A 14 1
A 12 22
A7 3
A6 4
A5 5
A4 6
A3 7
A2 8
A1 9
A 0 10
A 10 21
A 11 23
A 9 24
WRITE CONTROL
INPUT /W 27
CHIP SELECT
INPUT1 /S1 20
CHIP
SELECT
INPUT2
S2
22
32768 WORD
X 8BIT
(512 ROWS X
512 COLUMNS)
CLOCK
GENERATOR
11 DQ1
12 DQ2
13 DQ3
15 DQ4
16 DQ5
17 DQ6
18 DQ7
19 DQ8
DATA I/O
28 VCC
(5V)
14 GND
(0V)
MITSUBISHI
ELECTRIC
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