SMJ44C256 データシートの表示（PDF） - Austin Semiconductor

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SMJ44C256

262144 BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY

Austin Semiconductor 

SMJ44C256

262144 BY 4-BIT

DYNAMIC RANDOM-ACCESS MEMORY

SGMS034C – MAY 1989 – REVISED JUNE 1995

description

The SMJ44C256 series is a set of high-speed, 1 048 576-bit dynamic random access memories (DRAMs),

organized as 262 144 words of four bits each. These devices employ technology for high performance,

reliability, and low power.

These devices feature maximum RAS access times of 80 ns, 100 ns,120 ns, and 150 ns. Maximum power

dissipation is as low as 305 mW operating and 16.5 mW standby on 150-ns devices.

ICC peaks are 140 mA typical, and an input voltage undershoot of –1 V can be tolerated, minimizing system noise

considerations.

All inputs and outputs, including clocks, are compatible with Series 54 /174 TTL. All addresses and data-in lines

are latched on-chip to simplify system design. Data out is unlatched to allow greater system flexibility.

The SMJ44C256 is offered in 20-pin ceramic dual-in-line packages (JD suffix) and 20/26-terminal ceramic

leadless carriers (FQ / HL suffixes), 20/26-pin leaded carrier (HJ suffix), a 20-pin flatpack (HK suffix), and a

20-pin ceramic zig-zag in-line package (SV suffix). They are specified for operation from –55°C to125°C.

logic symbol†

6

A0

7

A1

8

A2

A3 9

11

A4

A5 12

13

A6

14

A7

A8 15

4

RAS

CAS 17

3

W

G 16

RAM 256K × 4

20D9/21D0

A

0

262 143

20D17/21D8

C20[ROW]

G23/[REFRESH ROW]

24[PWR DWN]

C21/[COLUMN]

G24

&

23C22

23,21D

G25

24,25EN

1

DQ1

DQ2 2

18

DQ3

DQ4 19

A,22D

∇ 26

A,Z26

† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the JD package.

2

• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443

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