AN209 データシートの表示（PDF） - Unspecified
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AN209 Datasheet PDF : 14 Pages
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AN 209: Using Terminator Technology in Stratix & Stratix GX Devices
Table 5 lists the DC current draw when using Terminator technology on-
chip parallel termination resistors for single-ended inputs or outputs.
Table 5. DC Current Draw for On-Chip Series-Parallel Termination (Input & Output Pins) Note (1)
Bank I/O Standard
Selected by Terminator
Technology
DC Current Draw per Pin for Series & Parallel Termination
(Ipin in mA) (2)
Output Mode
Input Mode
RS
GTL
N/A
GTL+
N/A
SSTL-2 class I
10
SSTL-2 class II
23
SSTL-3 class I
11
SSTL-3 class II
24
CTT
N/A
HSTL class I
N/A
HSTL class II
N/A
RT1 (3)
40
34
N/A
N/A
N/A
N/A
N/A (4)
N/A (4)
20
RT2 (3)
15
14
12
12
15
17
18
9
10
VCCIO (V)
3.3
3.3
2.5
2.5
3.3
3.3
3.3
1.5
1.5
Notes to Table 5:
(1) There are no current limitations for 1.8-V I/O standards (thermally-enhanced ball-grid array (BGA) cavity-up
packages).
(2) Ipin is the DC current drawn per pin.
(3) RT1 and RT2 are the parallel termination resistors for the voltage-referenced I/O standards. RT1is the parallel
termination resistor next to the output buffer and RT2 is the parallel termination resistor next to the input buffer. See
Figure 3.
(4) The CTT output buffer and HSTL Class I output buffer do not draw any current due to the on-chip termination
resistor for single-ended I/O pins, but they will still draw 8 mA as specified in the corresponding JEDEC
specifications.
8
Altera Corporation
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