AN1687 データシートの表示（PDF） - Motorola => Freescale

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AN1687

A FULL-FEATURED WIRELESS INTERFACE FOR RS-232 COMMUNICATIONS

Motorola => Freescale 

ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2005

AN1687

This encoding scheme allows for the representation of 256

unique data words and 256 unique control words. The control

byte $h00 is reserved and referred to as the idle byte.

When the Parallel–Input/Serial–Output (PISO) register is

ready to transmit a data byte (TXR asserted), a check is

made to see if real data has been transferred into the Serial

Communications Interface (SCI) data register of the MCU. If

data has been received, the data byte will be read, and the

initial state of D/C will be set to 1. If data has not been

received, the data byte will be set to $h00 (the idle byte) and

the initial state of D/C will be set to 0.

Next, the data byte is examined for a DC component. Each

0 bit of the data byte represents –1 and each 1 bit of the data

byte represents +1. All of these values are summed together:

a negative result indicates a low DC component, zero

indicates no DC component, and a positive (non–zero) result

indicates a high DC component. This component is

compared to a cumulative sum (which may be negative, zero,

or positive) and the following actions are taken:

If the current DC component sum is negative, and the

cumulative sum is positive or zero

OR

if the current DC component sum is positive or zero and the

cumulative sum is negative

THEN

clear the I bit (I=0). The new cumulative sum is equal to the

old cumulative sum plus the current sum.

OTHERWISE

set the I bit (I=1). The new cumulative sum is equal to the old

cumulative sum minus the current sum.

If the I bit is set, the contents of the data byte and D/C bit

are complemented.

The updated value of the I bit, data byte, and D/C bit are

placed on the PISO, and a transmission acknowledge signal

(NTXA) is asserted. Please note, the net effect of the DC

component contributed by the I and I bits and D/C and D/C

bits will always equal zero.

An analysis of this encoding scheme brings to light a few

interesting observations:

1. The average DC component over time will approach

zero.

2. The minimum frequency component which will be

observed in the data stream will equal 1/(2 x transmitted

bit period x 10).

3. The maximum (fundamental) frequency component

which will be observed in the data stream will equal 1/(2

x transmitted bit period).

4. A sequence of ten consecutive zeros or ones indicates

the presence of an idle byte.

Item 4 is perhaps the most interesting observation, since it

will allow the receiver to synchronize the incoming data and

align the serial stream on a byte–wide basis.

TRANSMITTING FREQUENCY for ENCODED DATA

For RS–232 communications which take the form of one

start bit, eight data bits, no parity, and one stop bit, the SCI

will receive 10 bits of data to represent one actual data byte.

For our encoding scheme, 12 bits must be transmitted for

each data or control byte received. If the transmit pipeline is

set to a frequency of at least 1.2 times the SCI receive

pipeline, the receive bandwidth will not have to be reduced

(i.e. no stop or hold conditions would be required).

In actual practice, the transmit pipeline was set to a

frequency 25% greater than the receive pipeline. As a result,

at a minimum, there will be at least one idle byte transmitted

for every 24 real data bytes. This useful feature allows the

receiver to re–synchronize from time to time.

ADDITIONAL FEATURES

As mentioned above, the opportunity presents itself to

transmit a control word (the idle byte just being a special case

of a control word) from time to time. With 255 control words

remaining, various special features can be built into the link,

all transparent to the actual RS–232 data communications.

One of the more obvious features which can be

implemented is hardware (RTS/CTS) flow control. The RTS

signal (for the baseset) and CTS signal (for the handset) can

be monitored and transmitted/received and interpreted by the

link. The latency will mostly be a function of the overhead

bandwidth.

Other features which can be implemented include, but are

not limited to:

Remote channel changing

Adaptive channel selection

Acknowledgments

DCD/DSR, etc. commands

CRC or other error checking

Half duplex handshaking

Power conservation modes

MOTOROLA SEMICONDUCTOR APPLICATION INFORMATION

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