AN2104 データシートの表示（PDF） - Freescale Semiconductor

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AN2104

Using Background Debug Mode for the M68HC12 Family

Freescale Semiconductor 

Operation

of Active BDM

AN2104

Freescale Semiconductor, Inc.

Application Note

Theory of Operation

BDMACT — Background Mode Active Status Bit

0 = BDM not active

1 = BDM active and waiting for serial commands

ENTAG — Instruction Tagging Enable Bit

Set by the TAGGO instruction and cleared when BDM is entered

0 = Tagging not enabled or BDM active

1 = Tagging active (BDM cannot process serial commands while

tagging is active.)

SDV — Shifter Data Valid Bit

Shows that valid data is in the serial interface shift register. Used by

firmware-based instructions.

0 = No valid data

1 = Valid data

TRACE

Asserted by the TRACE1 instruction

The second register of interest is the BDM CCR holding register. This

register contains the value of the CPU’s condition code register (CCR)

from the user’s program upon entering the BDM. See Figure 4.

Address: $FF06

Bit 7

6

5

4

3

2

1

Read:

CCR7

Write:

CCR6

CCR5

CCR4

CCR3

CCR2

CCR1

Reset: 0

0

0

0

0

0

0

Figure 4. BDM CCR Holding Register (CCRSAV)

Bit 0

CCR0

0

Here is a brief description of what transpires when going into the active

BDM:

• When the CPU gets the command to go into the BDM, the user’s

return address is stored in a temporary register.

• Next, the BDM ROM is turned on and the CPU fetches a vector

that points to the beginning of the BDM firmware program.

7

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