AN1816 データシートの表示（PDF） - Freescale Semiconductor

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AN1816

USING THE HC912B32 TO IMPLEMENT THE DISTRIBUTED SYSTEMS INTERFACE (DSI) PROTOCOL

Freescale Semiconductor 

Application Note

Freescale Semiconductor, Inc.

the slave draws additional current from the source during the bit time.

Conversely, no extra current is drawn when responding with a logic zero.

Figure 3 Current Waveform shows a representation of the current

waveform referenced to a voltage waveform.

Voltage

(from Master)

Logic 0

Logic 1

Logic 1

Logic 0

Current

(from Slave)

Logic 1

Logic 0

Logic 1

Logic 0

Figure 3 Current Waveform

Message

Format

Message

Encoding

DSI messages are composed of individual words separated by a

minimum frame delay. Transfers are full duplex, that is, command

messages from the master occur at the same time as responses from

the slaves. This is an important feature of the DSI as it doubles the

effective signal bandwidth. Slave responses to commands occur during

the next command message. This allows slaves time to decode the

command, act upon it and then respond to the master. The minimum

frame delay is present to allow recharge of energy storage devices in the

slaves. This is necessary because the slave receives its power from the

signal line.

Message encoding depends on the direction of the transfer. Command

and control messages are sent from the master to the slave. Response

messages are sent from the slaves to the master. In both cases there

are long word and short word messages. A long word consists of 16-bits

of information followed by a 4-bit cyclic redundancy check (CRC). A

short word is composed of 8-bits of information followed by the 4-bit

CRC.

AN1816

4

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