AN723 データシートの表示（PDF） - Vishay Semiconductors
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AN723 Datasheet PDF : 8 Pages
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AN723
Vishay Siliconix
For boost converters, the power stage behavior is more
complicated. Like buck converters, the low-frequency gain
varies according to the input/output condition. In addition,
there are two other factors of the boost power stage gain that
can be affected. The L-C double pole is a function of input/
output condition as shown in (6):
The divider resistor pair, R1 and R2 in Figures 2 and 3,
determine the output regulation point. Since R1 is part of the
compensation network, it is recommended to adjust R2 to
change the regulation voltage without affecting the loop gain.
With fixed R1, R2 can be easily calculated by (12) for the
desired output voltage setting.
fdouble – pole
=
-------------V-----I-N---------------
2πVOUT LC
(6)
As this double pole shifts to lower frequencies, the phase
delay also comes in at a lower frequency, making it difficult to
cross over with the same BW. Another troublesome feature of
boost power stages are their right-half-plane (RHP) zero,
which can create difficulties for power supply designers. This
RHP zero also varies with operating conditions as shown
in (7).
fRHP – zero
=
--------------V----I--N---2--------------
2πVOUTIOUTL
(7)
When high boost ratios and heavy loads are required, this
zero can move to low frequency. The negative effect of this is
that it results in gain boost with an extra phase delay that will
introduce instability into the loop gain. Designers must also
bear in mind the variation of dc/low frequency gain of a boost
converter as described in (8).
GDC
=
V-----O---U----T---2-
VIN
(8)
All these factors can change the loop response as line and
load conditions change. Hence, when good transient
response is required and a Type III network is used, the
component values need to be altered to compensate for these
changes. There are many was to accomplish this. Here is one
approach that lowers the entire loop gain to preserve a
stability margin. The feedback R4-C4 in series in Figure 7 can
be modified as
C4 = k ⋅ 1200pF
(9)
and
R4
=
-3---9---0---0--
k
Ω
(10)
where k = -----V----O----U---T---2-----
(11)
4.32 ⋅ VIN
C4 is used to adjust the gain at dc and low frequency, while R4
is also adjusted so that the zero created by C4-R4 stays at the
same frequency. The phase margin will diminish as load
current increases indefinitely, since the RHP zero will close in
to the crossover frequency. The design given in Figure 7 and
its adjustment in (9), (10), and (11) are good for 600-mA
loads, which is the maximum the Si9165 is designed for.
R2
=
---------R-----1---------
V-----O----U---T- – 1
(12)
VREF
The typical value for VREF is 1.3 V.
Layout Issues
One of the very few drawbacks of switching power supplies is
the noise level induced by their high-frequency switching
performance. Parasitic inductance and junction capacitance
become significant noise sources when a converter is
switching at megahertz frequencies. However, noise levels
can be minimized by properly laying out the components.
Here are some tips for laying out buck and boost converters
with the Si9165 controller.
• Minimize power traces. Since most power traces, in both
buck and boost converters, carry pulsating current, energy
stored in trace inductance during the pulse will be released
when the pulse current stops, causing high frequency
ringing with junction capacitor of the MOSFETs/diode or
even the input/output capacitor. Fortunately for Si9165
users, the MOSFETs are integrated into the IC, allowing
shortest trace between them. Designers will still need to
keep external power traces as short as possible, including
the trace from input/output capacitor to the switch, inductor
to switch, inductor to input/output capacitor, and, of course,
the ground trace.
• The decoupling capacitor VDD has to be as close as
possible to the pin to reduce the noise on this power source
for the internal logic circuit.
• The VS pin has to be close to input or output capacitor for
buck or boost converters, respectively, to provide enough
gate drive current without sacrificing much driving voltage. If
this creates an impossible layout situation, designers may
want to consider adding a 1-µF ceramic capacitor at the VS
pin, depending on the noise level.
• A high-frequency capacitor, normally a 0.1-µF ceramic
capacitor, is recommended across the sources of two
MOSFETs-right at the pins if possible-to reduce high-
frequency noise. The impedance of these capacitors is
lower at high frequencies compared with higher-value
capacitors.
• To keep the gate signal clean, they have to be placed away
from the inductor, since the alternating magnetic field is the
primary noise source in a switching converter.
See Si9165 buck and boost converter layout as examples.
FaxBack 408-970-5600, request 70823
6
www.siliconix.com
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