AN727 データシートの表示（PDF） - Vishay Semiconductors
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AN727 Datasheet PDF : 8 Pages
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AN727
Vishay Siliconix
With the Si9167, synchronization is possible without the use of
any extra components. With the external clock, the circuit
synchronizes during the falling edge. More than one Si9167
can be configured in a master-slave mode as shown in
Figure 9. The SYNC pin may also be driven from a very stable
external system clock signal, which locks the slave frequency
within a very tight tolerance. Although synchronization is
possible only during PWM, circuit performance is not affected
when either the master or slave is in PSM. (Switching
frequencies for master, slaves and CLK condition in PSM are
provided in Table 1.) In addition, since the SYNC is a
high-impedance gate, it does not load the CLK when it is in the
high state.
External
Clock
IC1
1
SD
20
COIL
2
19
PWM/PSM COIL
3
VIN
4
VIN
5
POK
18
PGND
17
COIL
16
PGND
6
SYNC
15
POKIN
7
CLK
8
GND
9
VREF
10
FB
14
VO
13
VDD
12
ROSC
11
COMP
Master
ROSC
IC2
1
SD
20
COIL
2
19
PWM/PSM COIL
3
VIN
4
VIN
5
POK
18
PGND
17
COIL
16
PGND
6
SYNC
15
POKIN
7
CLK
8
GND
9
VREF
10
FB
14
VO
13
VDD
12
ROSC
11
COMP
Slave
ROSC
IC3
1
SD
20
COIL
2
19
PWM/PSM COIL
3
VIN
4
VIN
5
POK
18
PGND
17
COIL
16
PGND
6
SYNC
15
POKIN
7
CLK
8
GND
9
VREF
10
FB
14
VO
13
VDD
12
ROSC
11
COMP
Slave
ROSC
FIGURE 9.
TABLE 1. MASTER AND SLAVE SWITCH FREQUENCIES DURING SYNCHRONIZATION
Mode
Switch Frequency
Master
Slave
Master
Slave
Master CLK Pin
PWM
PWM
CLK_Master
CLK_Master
PWM
PSM
CLK_Master
PSM_Slave
PSM
PWM
PSM_Master
CLK_Slave
High
PSM
PSM
PSM_Master
PSM_Slave
High
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Document Number: 70959
07-Jul-99
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