AN701 データシートの表示（PDF） - Vishay Semiconductors

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AN701

Designing High-Frequency DC-to-DC Converters With the Si9114A Switchmode Controller

Vishay Semiconductors 

S

Q

R

UV-Low

VCC

20 mA

SHUTDOWN

6

5

4

Si9114A

+OP

–OP

1

2

NC 3

TL431

AN701

Vishay Siliconix

Vout

Figure 3 Shutdown

PIN 2: SHUTDOWN

The shutdown pin is configured to allow fast latched

termination of the output pulse. The delay from shutdown to

output is typically 300 ns. This delay is short enough to allow

this pin to be used for over-voltage applications where fast

orderly shutdown is desirable: for example, when control of the

feedback loop is lost.

FBK

Using an opto-coupler and a TL431, interface is easy. (See 3)

Once latched, the shutdown can only be reset from the UVLO

NINV

circuit by re-cycling the power. In the event of an over-voltage,

the latch can be reset by momentarily pulling the VCC to a value

lower than the UVLO threshold.

This approach will generally be acceptable, since the

+

–

feedback winding will not be supplying power, and the only

power maintaining the latch will be supplied by the depletion

start transistor. Note, however, that this action will still be

subject to the power dissipation limits of the Si9114A package

and should ideally be applied as a short fast pulse.

An internal 20-mA current source pull-up on SHUTDOWN pin

Soft

is provided. However, if the Si9114A is used in a potentially

Star

noisy environment, a 10-kW pull-up is recommended from

SHUTDOWN to VCC to prevent fault triggering, and to prevent

a start-up problem when a fast slew rate power supply (dv/dt

> 100 V/ms) is used for +VIN (pin 1).

1.5 kW

Comp

PIN 3: REFERENCE

The reference voltage is a fully buffered band gap type which

can source 5 mA over the specified voltage tolerance range.

The reference should be well de-coupled to prevent instability

and jitter. A ceramic 100 nF or small tantalum is recommended,

depending on the de-coupling present on the supply pins.

Document Number: 70575

16-Jan-01

Figure 4 Operational Amplifier

PINS 4, 5 AND 6: ERROR AMPLIFIER

The error amplifier consists of a PMOS input folded cascade

gain stage followed by a class AB unity gain amplifier.

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