AN708 データシートの表示（PDF） - Vishay Semiconductors
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AN708 Datasheet PDF : 7 Pages
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AN708
Vishay Siliconix
For the present example:
Output power = 5.0 V x 1.5 A + 12 V x 0.15 A x 2 = 11.1 W
If efficiency is assumed to be 70%,
Input power = 11.1 W/0.7 = 15.86 W
For a little cushion, assume a low-input line voltage of 85 V ac.
Thus,
Vdc + 85 Ǹ2 + 120V dc.
Assuming a 20-V pk-pk input-capacitor ripple voltage the
minimum voltage is
Vmin = 120 V – 20 V = 100 V.
Iin = Pin/VDC
= 15.86 W/ 100 V = 0.1586 A
C+I
dt
dv
+
0.1586 A
20
x
V
0.01
s
= 79 mF
68 mF is a standard value. With 68 mF, the ripple voltage is
Vpp
+
I
dt
C
+
0.16
A 0.01
68E–6F
s
= 23.5 V, an acceptable value.
The capacitor voltage rating is calculated:
Vmax + 260 V ac x Ǹ2 + 368 V dc.
A 400-V capacitor is acceptable. A rating of 450-V dc is
preferable if high reliability is required or significant line
transients are expected.
Assuming a power factor of 0.65, the RMS input current is
Iac
+
Po
hac (PF)
+ (0.7)
11.1 W
(85 V) (0.65)
= 0.287 A
A 1-A bridge rectifier is more than adequate.
The primary inductance value is chosen by analyzing the
lowest input voltage case. For a given load, the value of the
peak transformer primary current will remain constant
regardless of the input voltage. Since the primary inductance
is fixed, the time to ramp to a given value of current is inversely
proportional to input voltage (V = Ldi/dt). Therefore, low line is
where the most time is needed to ramp to the desired primary
current. The duty factor limit dictates an on-time limit. After
Document Number: 70581
choosing an operating frequency and calculating the peak
primary current, a value for primary inductance, LP, can be
determined as follows:
For 100 kHz, period = 10 ms.
At 50% duty factor, ton(max) = 5 ms.
Ipk = Iin x 4
= (0.1586 A) (4)
= 0.634 A pk.
For VIN (dc) = 100 V
L+V
dt
Ipk
+
(100
V) (5E–6
0.634 A
s)
= 788 mH.
The actual inductance used was 735 mH. [For high-volume
production applications, the design engineer should consider
the worst case tolerances for clock frequency and inductor
value.]
See AN707 for transformer design equations and a fully
worked example.
The biggest considerations for universal input are related to
the additional insulation required to comply with VDE isolation
specifications. The physical space occupied by the insulation
typically reduces the useable fill factor to 25%. Furthermore,
the increase in leakage inductance caused by large physical
separation of the windings has the undesirable effects of
creating large voltage spikes on the power MOSFET drain,
contributing to power losses, and degrading load regulation.
Barrier tape at window ends will take up a lot of useable space,
so a core geometry with a long, low window should be selected
to minimize wasted area. This has the added benefit of
reducing leakage inductance. (See equation 6.4 of
reference 4.)
Wind the primary first. Apply the required insulation, and then
wind the secondaries. All secondaries should be wound
together with no intervening insulation, if voltage levels allow.
Optimal cross regulation is achieved in this way.
Further reductions in leakage inductance can be realized by
using interleaved windings. First wind one half of the primary,
followed by the secondaries and remaining primary turns. The
multiple primaries are usually connected in parallel. The spike
blanking circuit described in AN707 virtually eliminates the
primary-to-secondary leakage inductance problems, at least
from the standpoint of the regulation effects.
In selecting a power MOSFET, the main concerns will be the
rDS(on) and the drain voltage ratings. The transformer primary
voltage during the off time is VP = (Vo + VD) NP/NS. Using the
5-V winding,
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