AN708 データシートの表示（PDF） - Vishay Semiconductors
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AN708 Datasheet PDF : 7 Pages
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AN708
Vishay Siliconix
VP = (5.0 V + 0.4 V)(45 T/3 T) = 81
Therefore,
VDS(off) = VIN(max) + VP = 368 V + 81 V = 449 V.
A 600 V MOSFET allows for a 150 V spike due to leakage
inductance at high line. The RC snubber was sized empirically
to keep the peak drain voltage below 600 V.
The SMP4N60 is the smallest 600-V device available. At 25_C
the rDS(on) is 2.0 W. At 100_C, rDS(on) = 1.75 x 2 W = 3.5 W. The
peak drain current was previously calculated at 0.634 A. The
maximum RMS drain current is given by
ǒ Ǔ ǒǸ Ǔ 1
IRMS + Ipk
D
3
2
+ 0.634A
0.5
3
+ 0.26 A
On-state losses are given by
Pon = IRMS2 x rDS(on)
= (0.26 A)2 x 3.5 W
= 237 mW.
Switching losses are estimated at 350 mW. Since the thermal
resistance is specified at 80_C/W, a total temperature rise of
47_C is expected. This permits operation up to approximately
50_C ambient temperature, while holding the maximum
junction temperature to 100_C.
Something of more concern for universal-input than for a
single-input voltage supply is the range of duty factor to be
expected. Since the on time varies inversely with input voltage,
the high-line on-time can become quite small in a
high-frequency converter. For this kind of application, try to
keep the minimum on time to not much less than 1 ms. This will
help minimize noise problems with the current sense.
Also, be sure to use a non-inductive resistor for the current
sense (carbon composition or film type). Use of a wire-wound
resistor will produce large spikes which have to be filtered out.
The dual-delay current-limit comparators of the Si9120 will
frequently eliminate the need for a current-sense filter
altogether. The magnitude of the noise on the current sense
voltage will be affected by transformer parasitic capacitances
and PCB layout. As such, every design will exhibit slightly
different characteristics. Careful attention to detail in the
magnetics design and construction as well as the board layout
is a must.
For designs using current-sense resistors in the power
MOSFET’s source leg, note that the gate drive current is “seen”
by the sense resistor. In very low-power designs, this can
easily exceed the full load sense voltage causing severe noise
problems. Adding a fairly large-value gate resistor will help in
this case. Also, an RC current-sense filter becomes much
more important.
FOLDBACK CIRCUIT
Foldback current limiting is provided by Q3 and its associated
components. Under normal operating conditions, diode D6
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4
keeps C13 charged to VCC. Hence, Q3 is biased off. In the
event of a short circuit on any output, all winding voltages are
clamped low. This causes the voltage on C13 to drop to a level
set by divider R10 and R11. VCC is held at 8.6 V by the Si9120’s
start-up regulator. The current set by the value of R12 flows
through Q3 and R3, and causes the voltage on pin 4 to rise.
Since a peak threshold of 1.2 V is internally set on pin 4, the
voltage required across R5 to terminate a pulse is reduced by
an amount equal to the drop on R3.
ID = {1.2 - (IQ3)(R3)}/R5.
Thus as IQ3 increases, ID decreases.
See Figure 2a for foldback operating waveforms.
The foldback circuit will not perform correctly without the spike
blanking circuit. The leakage spike will peak charge C13 even
with a shorted load. However, the foldback function is
completely optional and all associated components can be
eliminated if a lower cost supply is desired.
TEST RESULTS
Data compiled on the test circuit appear in Table 1. Combined
line and load regulation measures "2.7%, well within a "5%
specification. Measured efficiency is 73.4% with no effort at
optimization. A detailed loss assessment could, no doubt, offer
some improvements. Pulse load tests show reasonable
transient response, and phase margin is measured at
60 degrees. For details on how to close the feedback loop,
refer to Vishay Siliconix application notes AN713 and AN707.
All data taken with dc input source to ensure stable readings.
TABLE 1. UNIVERSALĆINPUT SUPPLY
TEST DATA
Full Load:
VIN (dc)
100 V
200 V
300 V
385 V
Iin (mA)
143.9
72.3
48.9
39.4
+5 V
4.974
5.014
5.027
5.049
+12 V
12.64
12.76
12.79
12.81
–12 V
12.50
12.61
12.65
12.67
Half Load:
100 V
78.0
5.153
12.99
12.83
200 V
40.3
5.205
13.10
12.96
300 V
27.9
5.235
13.12
12.97
385 V
23.0
5.254
13.14
13.01
PKĆPK OUTPUT RIPPLE VOLTAGES
(SPIKES NOT INCLUDED)
5V
+12 V
–12 V
60 mV
45 mV
40 mV
Note: Worst case over full line-voltage range.
Document Number: 70581
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