AN709 データシートの表示（PDF） - Vishay Semiconductors

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AN709

Designing with the Si9976DY N-Channel Half-Bridge Driver and LITTLE FOOT® Dual MOSFETs

Vishay Semiconductors 

AN709

Vishay Siliconix

TABLE 1: RECOMMENDED VALUES

IN

High Side

G1

Part

Number

rDS(on)

Qg @

VGS = 10 V

(nC)

Minimum

Recommended

CBOOT (mF)

Logic

Si4946EY

0.055

30

Si9945

0.10

15

0.039

0.018

250 ns

Delay

Table 1 shows the selected bootstrap capacitor for each

MOSFET was selected using the method described, with a

switching frequency of 20 kHz.

If a shorter recharge time is required, an external signal diode

can be added from VDD to the positive side of the bootstrap

capacitor (CAP). This increases the charging current,

especially at the lower values of V+. Also, the value of the

capacitor on VDD should be increased, since this is the source

of the additional charging current.

The low-side drive circuitry operates directly from VDD and

does not have recharge requirements. The capacitor

connected to VDD supplies the charge required to turn on the

low-side MOSFET. It must be sized to ensure that VDD does

not drop below 14 V, which would trigger an undervoltage

condition. As in the case of the bootstrap capacitor, the VDD

bypass capacitor should be sized such that it will hold 10 times

the charge required by the MOSFET at a VGS = 10 V (C = 10

x Qg/VGS). The Si9945 requires a 15-nC charge for turn on with

VGS = 10 V. Therefore, a 0.018 mF capacitor will work well.

Since the requirements for value selection are the same as for

the bootstrap capacitor, the recommended values in Table 1

also apply to the VDD bypass capacitor. If an external bootstrap

diode is used to reduce the bootstrap capacitor recharge time,

the value of the VDD bypass capacitor should be doubled. This

compensates for the additional load of recharging the

bootstrap capacitor and prevents the occurrence of an

undervoltage condition.

CROSS CONDUCTION PROTECTION

Turn-on delays have been incorporated to prevent cross

conduction of the half-bridge MOSFETs (Figure 3). The

high-side MOSFET can be turned on only after a 250-ns time

delay, which is initiated by the low-side output, G2, switching

to ground. The low-side MOSFET can be turned on only after

a 300-ns delay which is initiated by the high-side control logic.

These delays prevent one half-bridge MOSFET from turning

on before the other is completely turned off. The difference in

the method of generating the delays occurs because the

high-side output, G1, is level shifted with respect to S1.

300 ns

Delay

G2

Low Side

EN

Logic

Figure 3. Cross Conduction Protection

UNDERVOLTAGE LOCKOUT

During power up, both MOSFETs are held off until the internal

power supply, VDD, is within approximately 0.7 V of the final

value, which is nominally 16 V. After power up, the low-side

undervoltage lockout circuitry, UVL2, continues to monitor

VDD. If an undervoltage condition occurs, both the high-side

and the low-side MOSFETs will be turned off, and the FAULT

output will be high. When the undervoltage condition no longer

exists, the FAULT output will be cleared and normal function

will resume.

A separate undervoltage lockout circuit, UVL1, monitors the

bootstrap voltage. If an undervoltage condition exists when the

IN line is switched high, this circuit will prevent the high-side

MOSFET from turning on. In addition, one of the following

conditions will exist. If S1 is high (as the result of inductive

flyback current through the high-side MOSFET’s body-drain

diode or a short from S1 to V+), the high-side MOSFET will be

allowed to turn on as soon as the undervoltage condition has

been removed. If S1 is low, the high-side MOSFET will be

allowed to turn on only after the undervoltage condition has

been removed and the IN line has been toggled low and back

to high.

SHORT CIRCUIT PROTECTION

If the load voltage, S1, does not make the intended transition

through ½ VDD to either ground or V+ before a specified time,

the Si9976DY sees this as an output short circuit (Figure 4).

The transition should take place in less than 300 ns for a

transition to V+, and 200 ns for a transition to ground. Detection

of a short circuit condition latches both outputs off and the fault

line high. The outputs are re-enabled by a rising edge on the

enable line, EN.

Document Number: 70582

15-Jun-00

www.vishay.com S FaxBack 408-970-5600

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