AN720 データシートの表示（PDF） - Silicon Laboratories

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AN720

PRECISION32 OPTIMIZATIONCONSIDERATIONS FOR CODESIZE ANDSPEED

Silicon Laboratories 

AN720

4.3. Alignment

In most cases, Cortex-M3 linkers place code in memory efficiently. In some projects, however, the alignment of

functions and code can be carefully managed manually to reduce code size or change code execution speed. For

example, if two functions in the same file call each other, but one ends up in flash and one ends up in RAM, the

compiler may need to place extra code to perform a long jump and take longer to execute that jump. If needed,

functions and variables can be explicitly located using scatterfiles and linker flags. More information on linker

scripts and scatterfiles can be found on the Code Red (http://support.code-red-tech.com/CodeRedWiki/

OwnLinkScripts) and ARM websites (http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.kui0101a/

armlink_babddhbf.htm).

4.4. RAM Size

The RAM size of a project can be just as important as the code size. In particular, the default configurations for

SiM3xxxx projects place the stack at the top of memory growing down and the heap at the end of program data

growing up. If too much of the RAM is used by program data, then the stack and heap may collide, leading to

difficult debugging issues in run-time. Projects should always leave enough RAM space to accommodate the

function-calling depth of the code.

4.5. SiM3xxxx Core and Flash Access Speed

At the maximum device AHB speed, an SiM3xxxx device reading flash every pipeline cycle may violate the

maximum flash access speed. To compensate for this, the FLASHCTRL module has controls to reduce the flash

access speed (SPMD and RDSEN). Depending on the code density and make-up (i.e., 16-bit or 32-bit

instructions), this may lead to stalls in the core before the next instructions can be fetched from flash. Executing at

high speeds with strings of 16-bit instructions may yield the fastest core operation.

4.6. SiM3xxxx Core and the Direct Memory Access (DMA) Module

On SiM3xxxx devices, the core and the DMA can access multiple AHB slaves at the same time without any

performance degradation. If the core and DMA access the same AHB slave at the same time (i.e., RAM), then the

AHB has priority-based arbitration in the following precedence:

1. Core data fetch

2. DMA

3. Core instruction fetch

If multiple DMA channels are active at the same time and accessing the same memory areas as the core, this

could lead to a reduction in core execution speed.

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