AN725 データシートの表示（PDF） - Silicon Laboratories

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AN725

ADVANCED LOW POWER TECHNIQUES FOR SiM3L1XX DEVICES

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AN725

5.2.4. Configuring a Device for Power Modes 2 and 6

For Power Modes 2 and 6, the core halts and no longer executes code, but the active peripherals still run from the

APB clock. The only difference between PM2 and PM6 is the APB clock speed (fast and slow, respectively).

To configure a device to run in PM2 or PM6:

1. Enable the clocks to peripherals that will be configured by firmware.

2. Select the desired clock source (LPOSC0, PLL0, etc.) and speed for both AHB and APB clocks.

3. Select the desired adaptive voltage scaling settings using the LDO module.

4. Disable Power Mode 8 in the Clock Control module.

5. (Optional) Disable the retention mode of any enabled RAM banks.

6. Set the pins in the lowest power configuration for this mode.

7. Set up the wakeup interrupt source (including priority).

8. Disable the SysTick timer to prevent these interrupts from waking the core.

9. Disable all unused peripherals.

10. Disable the clocks to all unused peripherals.

11. Jump to code in RAM.

12. Execute the DSB (Data Synchronization Barrier), ISB (Instruction Synchronization Barrier), and WFI (Wait

for Interrupt) or WFE (Wait for Event) instructions. For SiM3L1xx devices, WFI and WFE have the same

behavior.

To measure the data sheet numbers using an SiM3L1xx MCU Card and the AN725_PowerModes_2_and_6

example:

1. Configure the SiM3L1xx MCU Card according to the instructions in “5.2.1. Hardware Setup”.

2. Open the AN725_PowerModes_2_and_6 example in either Keil µVision or the Precision32 IDE.

3. Select the desired AHB clock rate using the #defines at the top of the file.

4. Compile and download the code to the device.

5. Disconnect the USB Debug Adapter.

6. Reset the device.

7. Press PB1.7 to place the device in PM2 or PM6. The PB1.5 LED will turn off.

8. Measure the power consumption of the device.

9. Press PB1.5 to wake the device from PM2 or PM6. When this happens, the PB1.7 LED will turn on and the

core will sit in an infinite while(1) loop.

The interrupt that wakes the core from the halted state must have sufficient priority if the WFI or WFE instruction

was called from within an ISR.

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Rev. 0.1

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