AN725 データシートの表示（PDF） - Silicon Laboratories

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AN725

ADVANCED LOW POWER TECHNIQUES FOR SiM3L1XX DEVICES

Silicon Laboratories 

AN725

4.4. Code Dependency

In addition to dynamic clock management, the power consumption of the SiM3L1xx device will vary with the type of

code the core executes. For example, if the core executes a complex math routine with branches, the pipeline will

miss every time a branch is taken and new instructions must be fetched. This stall and fetch period causes more

flash accesses, which increases power consumption. In addition, the core executes a wide variety of instructions

and activates the memory bus to fetch data from RAM or flash for use in these routines. In contrast, a string of NOP

instructions will take less power because the core isn’t executing complex instructions.

The data shown in Figure 2 does not use adaptive voltage scaling or any other techniques to change power

consumption. All of these measurements were taken using the PLL as the clock source with a higher SPMD setting

(i.e., reduced flash access frequency) at AHB frequencies above 40 MHz. The APB clock is equal to the AHB

clock, when the APB is enabled.

As shown by the data, the flash access frequency (SPMD) has a direct effect on the code that includes branches,

since the core stalls when waiting for the new instructions, resulting in reduced power consumption. This means

that it may be more efficient to run at a faster frequency with the same current consumption to reduce overall time

spent in active mode. For the code that is a long string of NOPs, the core never has a pipeline miss and never

stalls, so there is no change in power consumption with a different flash speed mode.

For power sensitive applications, experimenting with various code styles and instruction mixes may result in

reduced power consumption in active mode.

SPMD = 1 SPMD = 2

20

25

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35

40

45

50

AHB and APB Clock (MHz)

NOP code, no APB clocks enabled, all LDOs at 1.8 V

NOP code, all APB clocks enabled, all LDOs at 1.8 V

complex code, no APB clocks enabled, all LDOs at 1.8 V

complex code, all APB clocks enabled, all LDOs at 1.8 V

Figure 2. Power Consumption Code Dependency

Rev. 0.1

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