AN725 データシートの表示（PDF） - Silicon Laboratories

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AN725

ADVANCED LOW POWER TECHNIQUES FOR SiM3L1XX DEVICES

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AN725

To configure the converter for loads greater than 15 mA:

1. Power switch size set to 3 (PSMD = 3)

2. Synchronous mode enabled (ASYNCEN = 0)

3. Minimum pulse width disabled (MINPWSEL = 0)

Table 1 shows a summary of these settings for each load configuration.

Table 1. DC-DC Load Configurations

Load

Power Switch Size

(PSMD)

less than 5 mA

0

5 mA to 15 mA

0

greater than 15 mA

3

Synchronous or

Asynchronous

(ASYNCEN)

Asynchronous (1)

Synchronous (0)

Synchronous (0)

Minimum Pulse

Width (MINPWSEL)

40 ns (3)

disabled (0)

disabled (0)

After configuring the dc-dc converter for the load size, switch the appropriate LDOs to the converter output to

reduce system power. Each of the three LDOs (memory, digital, and analog) can be switched to the battery voltage

(VBAT) or the dc-dc converter output independently.

The firmware can adjust the dc-dc converter configuration based on the anticipated load for the active time. For

example, if only a few peripherals will be active and the core will halt for a period of time, then the load may be less

than 5 mA. Firmware can adjust the dc-dc converter appropriately during this period. If the core is fetching

instructions from flash at full speed and executing a math routine, then switching to the high load configuration will

yield lower power consumption.

For extremely light loads (less than 2-3 mA), the dc-dc converter will be less efficient than the LDOs at ~50%

efficiency, depending on the VBAT voltage and LDO bias settings. When this occurs, the dc-dc converter should be

bypassed (BEN = 1), which connects VBATDC to VDC, or disabled (DCDCEN = 0).

6

Rev. 0.1

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